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    • 1. 发明申请
    • RECONFIGURABLE PROCESSOR ARCHITECTURE
    • 可重构的处理器架构
    • WO2011107424A1
    • 2011-09-09
    • PCT/EP2011/052903
    • 2011-02-28
    • KARLSRUHER INSTITUT FÜR TECHNOLOGIEKÖNIG, RalfSTRIPF, TimoBECKER, Jürgen
    • KÖNIG, RalfSTRIPF, TimoBECKER, Jürgen
    • G06F15/78G06F15/80
    • G06F15/7867G06F15/8007
    • We propose a reconfigurable data processor architecture (1). Said processor architecture comprises: a first plurality of data processing elements (3; 3.1, 3.2,...), each of said first plurality of data processing elements comprising a respective synchronization unit, a data link structure (4) adapted for dynamically interconnecting a number of said data processing elements, at least one configuration register, and, preferably, at least one control unit (7) in operative connection with said configuration register for controlling a contents thereof, wherein, based on the contents of said configuration register, said first plurality of data processing elements (3; 3.1, 3.2,... ) is adapted for temporarily constituting at runtime at least one group (2) of one or more of said data processing elements from said first plurality of data processing elements dynamically via said data link structure, wherein said synchronization units are adapted for synchronizing data processing by individual data processing elements within said group of data processing elements. Said first plurality of data processing elements may be reconfigurably grouped and thus adapted to various data processing tasks at runtime. In this way, data processing efficiency may be greatly increased.
    • 我们提出一种可重构数据处理器架构(1)。 所述处理器架构包括:第一多个数据处理元件(3; 3.1,3.2,...),所述第一多个数据处理元件中的每一个包括相应的同步单元,适于动态互连的数据链路结构(4) 多个所述数据处理元件,至少一个配置寄存器,以及优选地,与所述配置寄存器操作连接的至少一个控制单元(7),用于控制其内容,其中,基于所述配置寄存器的内容, 所述第一多个数据处理元件(3; 3.1,3.2,...)适于在运行时临时构成来自所述第一多个数据处理元件的一个或多个所述数据处理元件的至少一个组(2) 经由所述数据链路结构,其中所述同步单元适于通过所述数据处理组e内的各个数据处理元件同步数据处理 lements。 所述第一多个数据处理元件可以被可重构地分组,并因此适于在运行时的各种数据处理任务。 以这种方式,可以大大提高数据处理效率。