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    • 1. 发明申请
    • PREPARING INSTRUCTION GROUPS IN A PROCESSOR HAVING MULTIPLE ISSUE PORTS
    • 在具有多个问题单位的处理者中准备指导小组
    • WO2006103395A1
    • 2006-10-05
    • PCT/GB2006/001000
    • 2006-03-17
    • TRANSITIVE LIMITEDLOVETT, William, OwenHAIKNEY, DavidEVANS, Matthew
    • LOVETT, William, OwenHAIKNEY, DavidEVANS, Matthew
    • G06F9/45
    • G06F9/3853G06F8/52G06F9/3885
    • During program code conversion, such as in a dynamic binary translator, automatic code generation provides target code (21) executable by a target processor (13). Multiple instruction ports (610) disperse a group of instructions to functional units (620) of the processor (13). Disclosed is a mechanism of preparing an instruction group (606) using a plurality of pools (700) having a hierarchical structure (711-715). Each pool (700) represents a different overlapping subset of the issue ports (610). Placing an instruction (600) into a particular pool (700) also reduces vacancies in any one or more subsidiary pools (700) in the hierarchy. In a preferred embodiment, a counter value (702) is associated with each pool (700) to track vacancies. A valid instruction group (606) is formed by picking the placed instructions (600) from the pools (700). The instruction groups are generated accurately and automatically. Decoding errors and stalls are minimised or completely avoided.
    • 在程序代码转换期间,例如在动态二进制转换器中,自动代码生成提供可由目标处理器(13)执行的目标代码(21)。 多个指令端口(610)将一组指令分散到处理器(13)的功能单元(620)。 公开了使用具有层次结构的多个池(700)来准备指令组(606)的机制(711-715)。 每个池(700)表示发布端口的不同重叠子集(610)。 将指令(600)放置到特定池(700)中也可以减少层级中任何一个或多个子池(700)中的空缺。 在优选实施例中,计数器值(702)与每个池(700)相关联以跟踪空位。 通过从池(700)拾取放置的指令(600)来形成有效指令组(606)。 指令组可以准确,自动地生成。 解码错误和失速被最小化或完全避免。