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1. 发明申请

WO2003007096A1 STATUS INDICATION DETECTION DEVICE AND METHOD 审中-公开
标题翻译：状态指示检测装置和方法
公开(公告)号：WO2003007096A1
公开(公告)日：2003-01-23
申请号：PCT/EP2002/007376
申请日：2002-07-03
申请人： TELEFONAKTIEBOLAGET LM ERICSSSON (publ) , ABENDROTH, Torsten , FLEER, Hans-Ulrich
发明人： ABENDROTH, Torsten , FLEER, Hans-Ulrich
IPC分类号： G05B19/4063
CPC分类号： H04L7/0012 , G05B19/0428 , G05B19/4063 , G05B2219/24026 , G05B2219/24056 , G05B2219/25039 , G05B2219/25258
摘要： A status indication detection apparatus (SIDM) comprises an input storage stage (INS), an intermediate storage stage (ISS) and an output storage stage (OSS). Status indications (IN STATUS) are input into the input register (INM) of the input stage (INS) and are shifted to the intermediate and to the output stage (ISS; OSS). The input and intermediate storage stages operate with a first reference clock (CLK-A) in a first clock domain (A) whilst the output storage stage operates with a different second reference clock (CLK-B) in the second clock domain (B). In accordance with the invention a reading out of the intermediate register (INT) of the intermediate stage (ISS) is only possible during the generation of a hold signal (LOCK) which keeps a current status indication in the intermediate storage stage (ISS) and blocks a transfer of a new status indication from the input stage (INS). Since the hold signal (LOCK) duration covers at lest one second clock reference period, a read out pulse (STROBE) can be placed within the hold signal duration (LOCKL). Thus, even at different phase and/or frequency relationships between the first and second reference clock (CLK-A, CLK-B) a metastability in the output register (ORM) can be avoided and no status indications output from the hardware device (HW) get lost.
摘要翻译：状态指示检测装置（SIDM）包括输入存储级（INS），中间存储级（ISS）和输出存储级（OSS）。状态指示（IN STATUS）被输入到输入级（INS）的输入寄存器（INM）中，并被移入中间级和输出级（ISS; OSS）。输入和中间存储级在第一时钟域（A）中以第一参考时钟（CLK-A）工作，而输出存储级在第二时钟域（B）中以不同的第二参考时钟（CLK-B）操作，。根据本发明，中间级（ISS）的中间寄存器（INT）的读出仅在生成保持中间存储级（ISS）中的当前状态指示的保持信号（LOCK）和阻止来自输入级（INS）的新状态指示的传送。由于保持信号（LOCK）持续时间至少覆盖一个第二时钟参考周期，读出脉冲（STROBE）可以被置于保持信号持续时间（LOCKL）内。因此，即使在第一和第二参考时钟（CLK-A，CLK-B）之间的不同相位和/或频率关系下，也可以避免输出寄存器（ORM）中的亚稳态，并且没有状态指示从硬件设备（HW ）走开。

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