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    • 1. 发明申请
    • ARCHITECTURAL SUPPORT FOR AUTOMATED ASSERTION CHECKING
    • 建筑支持自动检测
    • WO2011086034A1
    • 2011-07-21
    • PCT/EP2011/050153
    • 2011-01-07
    • INTERNATIONAL BUSINESS MACHINES CORPORATIONIBM UNITED KINGDOM LIMITEDELNOZAHY, Elmootazbellah, NabilSTEPHENSON, Mark, William
    • ELNOZAHY, Elmootazbellah, NabilSTEPHENSON, Mark, William
    • G06F11/36
    • G06F11/3692
    • A mechanism is provided for automatic detection of assertion violations. An application may write assertion tuples to the assertion checking mechanism. An assertion tuple forms a Boolean expression (predicate or invariant) that the developer of the application wishes to check. If the assertion defined by the tuple remains true, then the application does not violate the assertion. For any instruction that stores a value to a memory location or register at a target address, the assertion checking mechanism compares the target address to the addresses specified in the assertion tuples. If the target address matches one of the tuple addresses, then the assertion checking mechanism reads a value from the other address in the tuple. The assertion checking mechanism then recomputes the assertion using the retrieved value along with the value to be stored. If the assertion checking mechanism detects an assertion violation, the assertion checking mechanism raises an exception.
    • 提供了用于自动检测断言违规的机制。 应用程序可以将断言元组写入断言检查机制。 断言元组形成应用程序开发人员希望检查的布尔表达式(谓词或不变量)。 如果由元组定义的断言保持为真,则应用程序不会违反断言。 对于将值存储到存储器位置或在目标地址处注册的任何指令,断言检查机制将目标地址与断言元组中指定的地址进行比较。 如果目标地址与元组地址中的一个匹配,则断言检查机制从元组中的另一个地址读取一个值。 断言检查机制然后使用检索到的值重新计算断言以及要存储的值。 如果断言检查机制检测到断言违例,则断言检查机制引发异常。
    • 7. 发明申请
    • DEBUGGING MULTITHREADED CODE
    • 调试多项代码
    • WO2011131469A1
    • 2011-10-27
    • PCT/EP2011/055029
    • 2011-03-31
    • INTERNATIONAL BUSINESS MACHINES CORPORATIONIBM UNITED KINGDOM LIMITEDELNOZAHY, Elmootazbellah, NabilGHEITH, Ahmed
    • ELNOZAHY, Elmootazbellah, NabilGHEITH, Ahmed
    • G06F11/36
    • G06F9/3824G06F11/3636G06F11/3648
    • Mechanisms are provided for debugging application code using a content addressable memory. The mechanisms receive an instruction in a hardware unit of a processor of the data processing system, the instruction having a target memory address that the instruction is attempting to access. A content addressable memory (CAM) associated with the hardware unit is searched for an entry in the CAM corresponding to the target memory address. In response to an entry in the CAM corresponding to the target memory address being found, a determination is made as to whether information in the entry identifies the instruction as an instruction of interest. In response to the entry identifying the instruction as an instruction of interest, an exception is generated and sent to one of an exception handler or a debugger application. In this way, debugging of multithreaded applications may be performed in an efficient manner.
    • 提供了使用内容可寻址存储器调试应用程序代码的机制。 机构在数据处理系统的处理器的硬件单元中接收指令,该指令具有指令尝试访问的目标存储器地址。 搜索与硬件单元相关联的内容可寻址存储器(CAM),以对应于目标存储器地址的CAM中的条目。 响应于与所找到的目标存储器地址相对应的CAM中的条目,确定条目中的信息是否将该指令识别为感兴趣的指令。 响应于将该指令识别为感兴趣的指令的条目,生成异常并将其发送到异常处理程序或调试器应用程序之一。 以这种方式,可以以有效的方式执行多线程应用程序的调试。