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1. 发明申请

WO2012178140A1 POWER SUPPLY GENERATOR WITH NOISE CANCELLATION 审中-公开
标题翻译：具有噪声消除的电源发电机
公开(公告)号：WO2012178140A1
公开(公告)日：2012-12-27
申请号：PCT/US2012/043917
申请日：2012-06-24
申请人： QUALCOMM INCORPORATED , DAI, Liang , MATHE, Lennart Karl-Axel
发明人： DAI, Liang , MATHE, Lennart Karl-Axel
IPC分类号： H04B15/00 , H04B1/04
CPC分类号： H04B15/005 , H04B1/0475 , H04B1/0483
摘要： Techniques for performing noise cancellation/attenuation are disclosed. In one design, an apparatus includes a power supply generator having a switcher, a coupling circuit, an envelope amplifier, and a feedback circuit. The switcher generates DC and low frequency components and the envelope amplifier generates high frequency components of a supply voltage for a load, e.g., a power amplifier. The switcher receives a first supply voltage and provides a switcher output signal having switcher noise. The coupling circuit receives the switcher output signal and provides a first output signal having a first version of the switcher noise. The feedback circuit receives the switcher output signal and provides a feedback signal. The envelope amplifier receives an envelope signal and the feedback signal and provides a second output signal having a second version of the switcher noise, which is used to attenuate the first version of the switcher noise at the load.
摘要翻译：公开了用于执行噪声消除/衰减的技术。在一种设计中，一种设备包括具有切换器，耦合电路，包络放大器和反馈电路的电源发生器。切换器产生DC和低频分量，并且包络放大器产生负载（例如功率放大器）的电源电压的高频分量。切换器接收第一电源电压并提供具有切换器噪声的切换器输出信号。耦合电路接收切换器输出信号并提供具有第一版本的切换器噪声的第一输出信号。反馈电路接收切换器输出信号并提供反馈信号。包络放大器接收包络信号和反馈信号，并提供具有切换器噪声的第二版本的第二输出信号，其用于衰减负载处的切换器噪声的第一版本。

2. 发明申请

WO2007146590A3 DUTY CYCLE CORRECTION CIRCUIT 审中-公开
标题翻译：占空比校正电路
公开(公告)号：WO2007146590A3
公开(公告)日：2008-03-20
申请号：PCT/US2007069883
申请日：2007-05-29
申请人： QUALCOMM INC , DAI LIANG , NGUYEN LAM V
发明人： DAI LIANG , NGUYEN LAM V
IPC分类号： H03K5/156
CPC分类号： H03K5/1565
摘要： A duty cycle correction circuit capable of generating a clock signal having good (e.g., approximately 50%) duty cycle is described. The duty cycle correction circuit includes a clock deskew circuit and a duty cycle detection circuit. The clock deskew circuit receives an input clock signal that may have poor duty cycle, adjusts the input clock signal based on a control, and provides an output clock signal having an adjustable duty cycle. The duty cycle detection circuit detects error in the duty cycle of the output clock signal and generates the control in response to the detected error in the duty cycle. The clock deskew circuit and the duty cycle detection circuit implement a feedback loop that senses error in the duty cycle of the output clock signal and feeds back the control to correct the duty cycle error.
摘要翻译：描述了能够产生具有良好（例如大约50％）占空比的时钟信号的占空比校正电路。占空比校正电路包括时钟偏移电路和占空比检测电路。时钟偏移电路接收可能具有较差占空比的输入时钟信号，基于控制调整输入时钟信号，并提供具有可调占空比的输出时钟信号。占空比检测电路检测输出时钟信号的占空比误差，并响应于占空比中检测到的误差而产生控制。时钟去歪斜电路和占空比检测电路实现了一个反馈回路，其感测输出时钟信号的占空比中的误差并反馈控制以校正占空比误差。

3. 发明申请

WO2008089460A1 METHODS AND APPARATUS FOR DYNAMIC FREQUENCY SCALING OF PHASE LOCKED LOOPS FOR MICROPROCESSORS 审中-公开
标题翻译：用于微处理器的相位锁定灯的动态频率调节方法和装置
公开(公告)号：WO2008089460A1
公开(公告)日：2008-07-24
申请号：PCT/US2008/051520
申请日：2008-01-18
申请人： QUALCOMM Incorporated , DAI, Liang , LEWIS, Brandon Wayne , BRIDGES, Jeffrey Todd , CHEN, Weihua
发明人： DAI, Liang , LEWIS, Brandon Wayne , BRIDGES, Jeffrey Todd , CHEN, Weihua
IPC分类号： H03L7/189
CPC分类号： H03L7/189 , H03L2207/06
摘要： A phase-locked loop employing a plurality of oscillator complexes is disclosed. The phase-locked loop includes a clock output and a plurality of oscillator complexes operable to generate output signals. The phase-locked loop further includes control logic which is configured to selectively couple an output signal of one of the plurality of oscillator complexes to the clock output.
摘要翻译：公开了一种采用多个振荡器复合器的锁相环。锁相环包括时钟输出和可操作以产生输出信号的多个振荡器复合。锁相环还包括控制逻辑，其被配置为选择性地将多个振荡器复合体之一的输出信号耦合到时钟输出。

4. 发明申请

WO2010129824A1 ALL-DIGITAL SELECTABLE DUTY CYCLE GENERATION 审中-公开
标题翻译：全数字可选择的周期生成
公开(公告)号：WO2010129824A1
公开(公告)日：2010-11-11
申请号：PCT/US2010/033947
申请日：2010-05-06
申请人： QUALCOMM Incorporated , QUAN, Xiaohong , MATHE, Lennart K. , DAI, Liang , ALLADI, Dinesh J.
发明人： QUAN, Xiaohong , MATHE, Lennart K. , DAI, Liang , ALLADI, Dinesh J.
IPC分类号： H03K7/08 , H03K5/156
CPC分类号： H03K7/08 , H03K5/1565
摘要： All-digital techniques for generating periodic digital signals having selectable duty cycles. In one aspect, a computation block (210) is provided for computing the product of a selected duty cycle (C) and a discrete ratio (L) between a reference clock period and a high-frequency oscillator period. The computation block (210) may be coupled to a pulse width generator (220) for generating signals having pulse widths that are integer multiples of the high-frequency oscillator period (Tosc). In another aspect, a pulse width generator (220) may also accommodate mixed fractional multiples of high-frequency oscillator periods by tapping the individual inverter stages of a delay line matched to the individual inverter stages of a ring oscillator exemplary embodiment of the high-frequency oscillator.
摘要翻译：用于产生具有可选占空比的周期性数字信号的全数字技术。在一个方面，提供了一个计算块（210），用于计算一个基准时钟周期和一个高频振荡器周期之间的所选占空比（C）和离散比（L）的乘积。计算块（210）可以耦合到脉冲宽度发生器（220），用于产生具有作为高频振荡器周期（Tosc）的整数倍的脉冲宽度的信号。在另一方面，脉冲宽度发生器（220）还可以通过对与高频振荡器周期的环形振荡器示例性实施例的各个逆变器级相匹配的延迟线的各个逆变器级进行接收来适应高频振荡器周期的混合分数倍振荡器。

5. 发明申请

WO2007146590A2 DUTY CYCLE CORRECTION CIRCUIT 审中-公开
标题翻译：占空比校正电路
公开(公告)号：WO2007146590A2
公开(公告)日：2007-12-21
申请号：PCT/US2007/069883
申请日：2007-05-29
申请人： QUALCOMM Incorporated , DAI, Liang , NGUYEN, Lam V.
发明人： DAI, Liang , NGUYEN, Lam V.
IPC分类号： H03K5/156
CPC分类号： H03K5/1565
摘要： A duty cycle correction circuit capable of generating a clock signal having good (e.g., approximately 50%) duty cycle is described. The duty cycle correction circuit includes a clock deskew circuit and a duty cycle detection circuit. The clock deskew circuit receives an input clock signal that may have poor duty cycle, adjusts the input clock signal based on a control, and provides an output clock signal having an adjustable duty cycle. The duty cycle detection circuit detects error in the duty cycle of the output clock signal and generates the control in response to the detected error in the duty cycle. The clock deskew circuit and the duty cycle detection circuit implement a feedback loop that senses error in the duty cycle of the output clock signal and feeds back the control to correct the duty cycle error.
摘要翻译：描述了能够产生具有良好（例如大约50％）占空比的时钟信号的占空比校正电路。占空比校正电路包括时钟偏移电路和占空比检测电路。时钟偏移电路接收可能具有较差占空比的输入时钟信号，基于控制调整输入时钟信号，并提供具有可调占空比的输出时钟信号。占空比检测电路检测输出时钟信号的占空比误差，并响应于占空比中检测到的误差而产生控制。时钟去歪斜电路和占空比检测电路实现了一个反馈回路，其感测输出时钟信号的占空比中的误差并反馈控制以校正占空比误差。

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