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1. 发明申请

WO2009037684A3 SPARSE MATRIX BY VECTOR MULTIPLICATION 审中-公开
标题翻译：矢量矩阵的散列矩阵
公开(公告)号：WO2009037684A3
公开(公告)日：2010-05-06
申请号：PCT/IE2008000089
申请日：2008-09-19
申请人： TRINITY COLLEGE DUBLIN , GERAGHTY THOMAS DERMOT , GREGG DAVID , MCELROY BARTLEY , CONNOR FERGAL , MCELROY CIARAN
发明人： GERAGHTY THOMAS DERMOT , GREGG DAVID , MCELROY BARTLEY , CONNOR FERGAL , MCELROY CIARAN
IPC分类号： G06F17/16
CPC分类号： G06F17/16
摘要： The invention involves pre-processing the matrix according to an encoding scheme whereby the non-zero data (in any numerical format), blocking information, the row an column offset indices within a block are represented by state machine control words which are combined in a single data stream. Thus, a single vector may be used to store all of the matrix information required to compute a sparse matrix by vector multiplication. Therefore, the system can be used effectively with a single memory channel. Also, it can be used in parallel with multiple independent memory channels. This method of matrix-by-vector multiplication achieves allows very high FPU utilization to be achieved for low bandwidth matrices such as those from finite element calculations. Also, it allows local memory buffers to be simple, and so there is no need for a complex cache architecture.
摘要翻译：本发明涉及根据编码方案对矩阵进行预处理，由此非零数据（以任何数字格式）阻塞信息，行中的列偏移索引由状态机控制字表示，所述状态机控制字被组合在一个单数据流。因此，可以使用单个向量来存储通过向量乘法计算稀疏矩阵所需的所有矩阵信息。因此，可以使用单个存储器通道有效地使用该系统。此外，它可以与多个独立的存储器通道并行使用。这种逐向矢量乘法的方法实现了对于诸如来自有限元计算的低带宽矩阵来实现非常高的FPU利用率。此外，它允许本地内存缓冲区简单，因此不需要复杂的缓存架构。

2. 发明申请

WO2015071771A3 APPARATUS, SYSTEMS, AND METHODS FOR REMOVING NOISE FROM AN IMAGE 审中-公开
标题翻译：用于从图像中消除噪声的设备，系统和方法
公开(公告)号：WO2015071771A3
公开(公告)日：2015-11-12
申请号：PCT/IB2014003104
申请日：2014-11-17
申请人： LINEAR ALGEBRA TECHNOLOGIES LTD , DONOHOE DAVID , BARRY BRENDAN , MOLONEY DAVID , RICHMOND RICHARD , CONNOR FERGAL
发明人： DONOHOE DAVID , BARRY BRENDAN , MOLONEY DAVID , RICHMOND RICHARD , CONNOR FERGAL
IPC分类号： G06K9/40
CPC分类号： G06T5/002 , G06T2200/28 , G06T2207/20182 , H04N5/21 , H04N5/217
摘要： The disclosed embodiments include an apparatus implemented in a semiconductor integrated chip. The apparatus is configured to operate a composite function, comprising a first function and a second function, on a first patch of an image. The apparatus includes a first function operator configured to operate the first function on the group of pixel values to provide a first processed group of pixel values. The apparatus also includes a delay system configured to maintain the first processed group of pixel values for a predetermined period of time to provide a delayed processed group of pixel values. The apparatus further includes a second function operator configured to operate a second function on at least a second processed group of pixels and the delayed processed group to determine an output of the composite function.
摘要翻译：所公开的实施例包括在半导体集成芯片中实现的设备。该装置被配置为在图像的第一块上操作包括第一功能和第二功能的复合功能。该设备包括第一功能操作器，其被配置为对该组像素值操作第一功能以提供第一处理的像素值组。该设备还包括延迟系统，该延迟系统被配置为将第一处理的像素值组维持预定的时间段以提供经延迟处理的像素值组。该设备还包括第二功能操作器，其被配置为对至少第二处理的像素组和延迟处理的组进行操作以确定复合函数的输出的第二函数。

3. 发明申请

WO2015071771A2 APPARATUS, SYSTEMS, AND METHODS FOR REMOVING NOISE FROM AN IMAGE 审中-公开
标题翻译：用于从图像中去除噪声的装置，系统和方法
公开(公告)号：WO2015071771A2
公开(公告)日：2015-05-21
申请号：PCT/IB2014/003104
申请日：2014-11-17
申请人： LINEAR ALGEBRA TECHNOLOGIES LIMITED , DONOHOE, David , BARRY, Brendan , MOLONEY, David , RICHMOND, Richard , CONNOR, Fergal
发明人： DONOHOE, David , BARRY, Brendan , MOLONEY, David , RICHMOND, Richard , CONNOR, Fergal
IPC分类号： G06T5/00 , H04N5/217
CPC分类号： G06T5/002 , G06T2200/28 , G06T2207/20182 , H04N5/21 , H04N5/217
摘要： The disclosed embodiments include an apparatus implemented in a semiconductor integrated chip. The apparatus is configured to operate a composite function, comprising a first function and a second function, on a first patch of an image. The apparatus includes a first function operator configured to operate the first function on the group of pixel values to provide a first processed group of pixel values. The apparatus also includes a delay system configured to maintain the first processed group of pixel values for a predetermined period of time to provide a delayed processed group of pixel values. The apparatus further includes a second function operator configured to operate a second function on at least a second processed group of pixels and the delayed processed group to determine an output of the composite function.
摘要翻译：所公开的实施例包括在半导体集成芯片中实现的装置。该装置被配置为在图像的第一块上操作包括第一功能和第二功能的复合功能。该装置包括第一功能操作器，其被配置为对该组像素值操作第一功能以提供第一处理的像素值组。该装置还包括延迟系统，其被配置为在预定时间段内保持第一经处理的像素值组以提供延迟处理的像素值组。该装置还包括第二功能操作器，其被配置为在至少第二处理的像素组和延迟处理的组上操作第二功能以确定复合功能的输出。

4. 发明申请

WO2009037684A2 SPARSE MATRIX BY VECTOR MULTIPLICATION 审中-公开
标题翻译：矢量矩阵的散列矩阵
公开(公告)号：WO2009037684A2
公开(公告)日：2009-03-26
申请号：PCT/IE2008/000089
申请日：2008-09-19
申请人： PROVOST FELLOWS AND SCHOLARS OF THE COLLEGE OF THE HOLY AND UNDIVIDED TRINITY OF QUEEN ELIZABETH NEAR DUBLIN , GERAGHTY, Thomas, Dermot , GREGG, David , McELROY, Bartley , CONNOR, Fergal , McELROY, Ciarán
发明人： GERAGHTY, Thomas, Dermot , GREGG, David , McELROY, Bartley , CONNOR, Fergal , McELROY, Ciarán
IPC分类号： G06F17/16
CPC分类号： G06F17/16
摘要： The invention involves pre-processing the matrix according to an encoding scheme whereby the non-zero data (in any numerical format), blocking information, the row an column offset indices within a block are represented by state machine control words which are combined in a single data stream. Thus, a single vector may be used to store all of the matrix information required to compute a sparse matrix by vector multiplication. Therefore, the system can be used effectively with a single memory channel. Also, it can be used in parallel with multiple independent memory channels. This method of matrix-by-vector multiplication achieves allows very high FPU utilization to be achieved for low bandwidth matrices such as those from finite element calculations. Also, it allows local memory buffers to be simple, and so there is no need for a complex cache architecture.
摘要翻译：本发明涉及根据编码方案对矩阵进行预处理，由此非零数据（以任何数字格式）阻塞信息，行中的列偏移索引由状态机控制字表示，所述状态机控制字被组合在一个单数据流。因此，可以使用单个向量来存储通过向量乘法计算稀疏矩阵所需的所有矩阵信息。因此，可以使用单个存储器通道有效地使用该系统。此外，它可以与多个独立的存储器通道并行使用。这种逐向矢量乘法的方法实现了对于诸如来自有限元计算的低带宽矩阵来实现非常高的FPU利用率。此外，它允许本地内存缓冲区简单，因此不需要复杂的缓存架构。

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