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1. 发明申请

WO2012026957A1 POWER AND AREA EFFICIENT INTERLEAVED ADC 审中-公开
标题翻译：功率和面积有效的交互式ADC
公开(公告)号：WO2012026957A1
公开(公告)日：2012-03-01
申请号：PCT/US2010/061546
申请日：2010-12-21
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED , BRIGHT, William, J. , PAYNE, Robert, F.
发明人： BRIGHT, William, J. , PAYNE, Robert, F.
IPC分类号： H03M1/12
CPC分类号： H03M1/1215 , H03M1/1225 , H03M1/164 , H03M1/44
摘要： Pipeline analog-to-digital converters (ADCs) are commonly used for high frequency applications; however, operating at high sampling rates will often result in high power consumption or tight timing constraints. Here, though, an ADC is provided that allows for relaxed timing (which enables a high sampling rate) with low power consumption. This is accomplished through the use of multiplexed, front-end track- and-hold (T/H) circuits that sample on non-overlapping portions of a clocking signal in conjunction with "re-used" or shared analog processing circuitry. Parallel track- and-hold (T/H) circuits (304, 306) receive an analog input signal (AIN or prior residue) and are clocked at half clock cycles (CLK/2) by clocking circuit 303 to sample/hold on non- overlapping logic phases. The T/H circuits (304, 306) are respectively coupled to analog-to-digital converter (ADC 310) through multiplexer (308) and to digital-to-analog converter (DAC 312), adder (314) and amplifier (316) to perform analog processing to resolve sampled signals for digital output circuit (104) and to generate a residue signal (ROUT).
摘要翻译：管道模数转换器（ADC）通常用于高频应用; 然而，以高采样率运行通常会导致高功耗或严格的时序限制。然而，在这里，提供了允许具有低功耗的轻松定时（其实现高采样率）的ADC。这通过使用多路复用的前端跟踪和保持（T / H）电路来实现，该电路在“重用”或共享的模拟处理电路的同时在时钟信号的非重叠部分上进行采样。并行跟踪和保持（T / H）电路（304,306）接收模拟输入信号（AIN或先前残差），并且通过计时电路303以半个时钟周期（CLK / 2）计时，以对其进行采样/保持 - 重叠逻辑阶段 T / H电路（304,306）分别通过多路复用器（308）和数模转换器（DAC312），加法器（314）和放大器（316）耦合到模拟 - 数字转换器）执行模拟处理以解码用于数字输出电路（104）的采样信号并产生残留信号（ROUT）。

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