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1. 发明申请

WO2014105197A1 HETEROGENEOUS PROCESSOR APPARATUS AND METHOD 审中-公开
标题翻译：异构处理器装置和方法
公开(公告)号：WO2014105197A1
公开(公告)日：2014-07-03
申请号：PCT/US2013/048352
申请日：2013-06-27
申请人： INTEL CORPORATION , NARVAEZ, Paolo , SRINIVASA, Ganapati, N. , GORBATOV, Eugene , SUBBAREDDY, Dheeraj, R. , NAIK, Mishali , NAVEH, Alon , PRABHAKARAN, Abirami , WEISSMANN, Eliezer , KOUFATY, David, A. , BRETT, Paul , HAHN, Scott, D. , HERDRICH, Andrew, J. , SODHI, Inder, M. , KHANNA, Gaurv , FENGER, Russel, J. , BIGBEE, Bryant, E. , HENROID, Andrew D.
发明人： NARVAEZ, Paolo , SRINIVASA, Ganapati, N. , GORBATOV, Eugene , SUBBAREDDY, Dheeraj, R. , NAIK, Mishali , NAVEH, Alon , PRABHAKARAN, Abirami , WEISSMANN, Eliezer , KOUFATY, David, A. , BRETT, Paul , HAHN, Scott, D. , HERDRICH, Andrew, J. , SODHI, Inder, M. , KHANNA, Gaurv , FENGER, Russel, J. , BIGBEE, Bryant, E. , HENROID, Andrew D.
IPC分类号： G06F9/38 , G06F9/46
CPC分类号： G06F9/3891
摘要： A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of large physical processor cores to software through a corresponding set of virtual cores and to hide the set of small physical processor core from the software.
摘要翻译：描述异构处理器架构。例如，根据本发明的一个实施例的处理器包括：一组大的物理处理器核心; 一组具有相对较低性能处理能力的小物理处理器核和相对于大型物理处理器核的相对较低的功率使用; 虚拟到物理（V-P）映射逻辑，以通过相应的一组虚拟核心将大型物理处理器核心集合暴露给软件，并从该软件中隐藏小型物理处理器核心集。

2. 发明申请

WO2014105174A1 HETEROGENEOUS PROCESSOR APPARATUS AND METHOD 审中-公开
标题翻译：异构处理器装置和方法
公开(公告)号：WO2014105174A1
公开(公告)日：2014-07-03
申请号：PCT/US2013/047700
申请日：2013-06-25
申请人： INTEL CORPORATION , NARVAEZ, Paolo , SRINIVASA, Ganapati, N. , GORBATOV, Eugene , SUBBAREDDY, Dheeraj, R. , NAIK, Mishali , NAVEH, Alon , PRABHAKARAN, Abirami , WEISSMANN, Eliezer , KOUFATY, David, A. , BRETT, Paul , HAHN, Scott, D. , HERDRICH, Andrew, J. , KHANNA, Gaurav , FENGER, Russell, J. , BIGBEE, Bryant, E. , HENROID, Andrew, D.
发明人： NARVAEZ, Paolo , SRINIVASA, Ganapati, N. , GORBATOV, Eugene , SUBBAREDDY, Dheeraj, R. , NAIK, Mishali , NAVEH, Alon , PRABHAKARAN, Abirami , WEISSMANN, Eliezer , KOUFATY, David, A. , BRETT, Paul , HAHN, Scott, D. , HERDRICH, Andrew, J. , KHANNA, Gaurav , FENGER, Russell, J. , BIGBEE, Bryant, E. , HENROID, Andrew, D.
IPC分类号： G06F9/44
CPC分类号： G06F9/45558 , G06F9/3885 , G06F9/5077 , G06F2009/4557
摘要： A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of two or more small physical processor cores; at least one large physical processor core having relatively higher performance processing capabilities and relatively higher power usage relative to the small physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of two or more small physical processor cores to software through a corresponding set of virtual cores and to hide the at least one large physical processor core from the software.
摘要翻译：描述异构处理器架构。例如，根据本发明的一个实施例的处理器包括：一组两个或更多个小物理处理器核; 至少一个大型物理处理器核具有相对较高性能的处理能力和相对较小的物理处理器核的相对较高的功率使用; 虚拟到物理（V-P）映射逻辑，以通过相应的一组虚拟核心将两个或更多个小型物理处理器核心的集合暴露给软件，并从软件中隐藏至少一个大型物理处理器核心。

3. 发明申请

WO9909510A3 MEMORY ATTRIBUTE PALETTE 审中-公开
标题翻译：内存属性PALETTE
公开(公告)号：WO9909510A3
公开(公告)日：1999-05-14
申请号：PCT/US9815054
申请日：1998-07-21
申请人： INTEL CORP , HACKING LANCE E , BIGBEE BRYANT E , SHAHIDZADEH SHAHROKH , THAKKAR SHREEKANT S
发明人： HACKING LANCE E , BIGBEE BRYANT E , SHAHIDZADEH SHAHROKH , THAKKAR SHREEKANT S
IPC分类号： G06F12/10 , G06F12/08 , G06F12/00 , G06F12/02
CPC分类号： G06F12/0802
摘要： The present invention relates to a computer system in which linear memory attributes (60) are specified. Physical memory attributes may also be specified in physical attribute registers (84). A memory attribute palette (MAP) (50) receives index signals and selects linear memory attributes in response to the index signals. An effective memory attribute selector (88) receives selected linear memory attribute signals and, if present, the physical memory attribute signals and, in response thereto, selects effective memory attribute signals to present an effective memory attribute. In a preferred embodiment, the linear memory attributes may be programmably written into one or more registers, thereby allowing a program or OS flexibility in the choice of memory attributes, including memory attributes not currently used. The invention allows a program to apply a memory attribute of choice to a particular section of memory, thereby allowing the computer system to provide higher performance.
摘要翻译：本发明涉及一种其中规定了线性存储器属性（60）的计算机系统。物理存储器属性也可以在物理属性寄存器中指定（84）。存储器属性调色板（MAP）（50）接收索引信号并响应于索引信号选择线性存储器属性。有效存储器属性选择器（88）接收所选择的线性存储器属性信号，并且如果存在物理存储器属性信号，并且响应于此选择有效存储器属性信号以呈现有效的存储器属性。在优选实施例中，线性存储器属性可以可编程地写入一个或多个寄存器，从而允许程序或OS灵活地选择存储器属性，包括当前未使用的存储器属性。本发明允许程序将选择的存储器属性应用于存储器的特定部分，从而允许计算机系统提供更高的性能。

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