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1. 发明申请

WO2006056757A1 SOLAR ENERGY TRAP AND TURBINE 审中-公开
标题翻译：太阳能能源和涡轮机
公开(公告)号：WO2006056757A1
公开(公告)日：2006-06-01
申请号：PCT/GB2005/004477
申请日：2005-11-22
申请人： ARKAS, Evangelos , ARKAS, Nicholas
发明人： ARKAS, Evangelos , ARKAS, Nicholas
IPC分类号： F24J2/10 , F24J2/04 , F02C1/05 , F03G6/00 , F03G6/06 , F23G1/00
CPC分类号： F23G5/08 , F02C1/05 , F03G6/005 , F03G6/067 , F23G1/00 , F23G2900/50803 , F24S10/70 , F24S23/70 , F24S70/60 , F24S2023/88 , Y02E10/44 , Y02E10/46 , Y02E20/12
摘要： A solar energy turbine includes solar energy trap (1110) having a chamber with an inlet port (12), such that solar energy (13) entering the chamber through the inlet port is absorbed and reflected within the chamber means until substantially all the solar energy is absorbed by the chamber. Preferably, the inlet port is arranged to cause photons of the solar energy entering the chamber to circulate substantially in a single direction within the chamber until absorbed, such that on re-passing the inlet port substantially no photons emerge from the inlet port. The solar energy turbine includes a heat exchanger (1150, 1160, 1170) for extracting energy from the solar energy trap to drive a turbine (1120).
摘要翻译：太阳能涡轮机包括太阳能捕集器（1110），其具有具有入口端口（12）的腔室，使得通过入口进入腔室的太阳能（13）在腔室装置内被吸收并反射直到基本上所有的太阳能被房间吸收。优选地，入口端口被布置成使得进入腔室的太阳能的光子基本上在腔室内的单个方向上循环，直到被吸收，使得在重新通过入口端口时基本上没有光子从入口出射。太阳能涡轮机包括用于从太阳能捕集器提取能量以驱动涡轮机（1120）的热交换器（1150,1160,1170）。

2. 发明申请

WO03012995A2 PULSE PEAK AND/OR TROUGH DETECTOR 审中-公开
标题翻译：脉冲峰值和/或粗糙探测器
公开(公告)号：WO03012995A2
公开(公告)日：2003-02-13
申请号：PCT/GB0203332
申请日：2002-07-18
申请人： DAIDALOS INC , ARKAS DR EVANGELOS , ARKAS NICHOLAS
发明人： ARKAS DR EVANGELOS , ARKAS NICHOLAS
IPC分类号： H03K5/1532 , H03K5/1534 , H03K5/00
CPC分类号： H03K5/1532 , H03K5/1534
摘要： A pulse detector (100, 200) has a leading edge detector and a trailing edge detector. A timing circuit (300) is provided for determining the pulse duration between the leading edge and the trailing edge of a signal pulse; and a divider (170) divides the pulse duration to produce a first timing pulse representative of a mid-point or peak of the signal pulse. An inventer (210) may also be provided to produce a second timing pulse representative of troughs between signal pulses. A combiner (410) may optionally be provided for combining the first and second timing pulses. The detector has application in signal cleaning circuits.
摘要翻译：脉冲检测器（100,200）具有前沿检测器和后沿检测器。定时电路（300）被提供用于确定信号脉冲的前沿和后沿之间的脉冲持续时间; 和分频器（170）分割脉冲持续时间以产生表示信号脉冲的中点或峰值的第一定时脉冲。发明人（210）也可以被提供以产生表示信号脉冲之间的波谷的第二定时脉冲。可以可选地提供组合器（410）以组合第一和第二定时脉冲。该检测器可用于信号清洁电路。

3. 发明申请

WO1997016901A1 CLOCK SIGNAL CLEANING CIRCUIT 审中-公开
标题翻译：时钟信号清除电路
公开(公告)号：WO1997016901A1
公开(公告)日：1997-05-09
申请号：PCT/CA1996000706
申请日：1996-10-24
申请人： ADVANCED INTELLIGENCE INC. , ARKAS, Evan , ARKAS, Nicholas
发明人： ADVANCED INTELLIGENCE INC.
IPC分类号： H04L07/02
CPC分类号： H04L7/0066 , H03K5/1252 , H04L7/0083 , H04L7/027 , H04L7/0337
摘要： A device which reduces jitter and narrows the frequency spectrum of a jitter-ridden clock signal includes a basic unit having a plurality of series connected delay elements outputs from each delay element are all connected to an AND/NAND gate. A front end of the device locates missing clock pulses and ensures regular clock pulses are relayed to the remainder of the device. A succeeding section including plural basic units hones the signal such that jitter elements are removed. By the output of this section time duty cycles are uneven, a positive edge triggered flip-flop is then used to obtain 50 % duty cycles at the expense of halving the clock signal's frequency. Optionally a frequency doubler can be employed to regain the clock signal's original frequency.
摘要翻译：降低抖动并使抖动时钟信号的频谱变窄的装置包括具有多个串联连接的延迟元件的基本单元，每个延迟元件的输出都连接到与/非门。器件的前端定位丢失的时钟脉冲，并确保常规时钟脉冲被中继到器件的其余部分。包括多个基本单元的后续部分使信号松动以使抖动元件被去除。通过本节的输出，时间占空比不均匀，然后使用正沿触发触发器以牺牲时钟信号频率的一半为代价获得50％的占空比。可以选择使用倍频器来重新获得时钟信号的原始频率。

4. 发明申请

WO2006021752A1 SOLAR ENERGY TRAP 审中-公开
标题翻译：太阳能能量捕捉
公开(公告)号：WO2006021752A1
公开(公告)日：2006-03-02
申请号：PCT/GB2005/003220
申请日：2005-08-17
申请人： ARKAS, Evangelos , ARKAS, Nicholas
发明人： ARKAS, Evangelos , ARKAS, Nicholas
IPC分类号： F24J2/07
CPC分类号： F24S70/12 , F24S20/20 , F24S23/12 , F24S23/70 , F24S70/20 , F24S2023/88 , Y02E10/41
摘要： A solar energy trap (10) includes a chamber (11) having inlet post (12), such that solar energy (13) entering the chamber (11) through the inlet port (12) is absorbed and reflected within the chamber (11) means until substantially all the solar energy (13) is absorbed by the chamber (11). Preferably, the inlet port (12) is arranged to cause photons of the solar energy (13) entering the chamber (11) to circulate substantially in a single direction within the chamber (11) until absorbed, such that on re-passing the inlet port (12) substantially no photons emerge from the inlet port (12).
摘要翻译：太阳能捕集器（10）包括具有入口柱（12）的室（11），使得通过入口（12）进入室（11）的太阳能（13）在室（11）内被吸收和反射，意味着直到基本上所有的太阳能（13）被腔室（11）吸收。优选地，入口端口（12）被布置成使得进入腔室（11）的太阳能（13）的光子基本上在腔室（11）内的单个方向上循环直到吸收，使得在重新通过入口端口（12）基本上没有光子从入口（12）出射。

5. 发明申请

WO2004068718A8 PERIOD-TO-DIGITAL CONVERTER 审中-公开
标题翻译：周期到数字转换器
公开(公告)号：WO2004068718A8
公开(公告)日：2004-10-28
申请号：PCT/GB2004000341
申请日：2004-01-27
申请人： ARKAS EVANGELOS , ARKAS NICHOLAS
发明人： ARKAS EVANGELOS , ARKAS NICHOLAS
IPC分类号： H03M1/14 , H03M1/50
CPC分类号： G04F10/005
摘要： A period-to-digital converter includes a clock (1) for generating a timing signal, delay lines (2) for producing cumulatively incrementally delayed timing signals for each cycle of the timing signal and an isolator (3) connected in parallel to the delay lines for generating a signal indicative of a number of partial cycles of the timing signal corresponding to which of the incrementally delayed timing signals last contained a specific feature. First and second counters (5, 8) connected to the isolator are enabled for successive time periods to be measured and first and second latches (11, 12) respectively connected to the first and second counters are latched at the end of alternate successive time periods respectively. An arithmetic module (22) connected to the first and second latches obtains difference values between their output values, which difference values are representative of the successive time periods respectively.
摘要翻译：周期数字转换器包括用于产生定时信号的时钟（1），用于产生用于定时信号的每个周期的累积递增延迟的定时信号的延迟线（2）和与延迟并联连接的隔离器（3）用于产生指示与最后包含特定特征的增量延迟的定时信号中的哪一个对应的定时信号的部分周期数的信号的线。连接到隔离器的第一和第二计数器（5,8）被启用以测量连续的时间段，并且分别连接到第一和第二计数器的第一和第二锁存器（11,12）在交替的连续时间段的结束时被锁存分别。连接到第一和第二锁存器的算术模块（22）获得它们的输出值之间的差值，该差分值分别表示连续的时间段。

6. 发明申请

WO2003012995A3 PULSE PEAK AND/OR TROUGH DETECTOR 审中-公开
公开(公告)号：WO2003012995A3
公开(公告)日：2003-02-13
申请号：PCT/GB2002/003332
申请日：2002-07-18
申请人： DAIDALOS, INC. , ARKAS, DR EVANGELOS , ARKAS, Nicholas
发明人： ARKAS, DR EVANGELOS , ARKAS, Nicholas
IPC分类号： H03K5/153
摘要： A pulse detector (100, 200) has a leading edge detector and a trailing edge detector. A timing circuit (300) is provided for determining the pulse duration between the leading edge and the trailing edge of a signal pulse; and a divider (170) divides the pulse duration to produce a first timing pulse representative of a mid-point or peak of the signal pulse. An inventer (210) may also be provided to produce a second timing pulse representative of troughs between signal pulses. A combiner (410) may optionally be provided for combining the first and second timing pulses. The detector has application in signal cleaning circuits.

7. 发明申请

WO2004068718A1 PERIOD-TO-DIGITAL CONVERTER 审中-公开
标题翻译：周期到数字转换器
公开(公告)号：WO2004068718A1
公开(公告)日：2004-08-12
申请号：PCT/GB2004/000341
申请日：2004-01-27
申请人： ARKAS, Evangelos , ARKAS, Nicholas
发明人： ARKAS, Evangelos , ARKAS, Nicholas
IPC分类号： H03M1/14
CPC分类号： G04F10/005
摘要： A period-to-digital converter includes a clock (1) for generating a timing signal, delay lines (2) for producing cumulatively incrementally delayed timing signals for each cycle of the timing signal and an isolator (3) connected in parallel to the delay lines for generating a signal indicative of a number of partial cycles of timing signal corresponding to which to the incrementally delayed timing signals last contained a specific feature. First and second counters (5, 8) connected to the isolator are enabled for successive time periods to be measured and the first and second latches (11, 12) respectively connected to the first and second counters are latched at the end of alternate successive time periods respectively. An arithmetic module (22) connected to the first and second latches obtains difference values between their output values, which difference values are representative of the successive time periods respectively.
摘要翻译：周期数字转换器包括用于产生定时信号的时钟（1），用于产生用于定时信号的每个周期的累积递增延迟的定时信号的延迟线（2）和与延迟并联连接的隔离器（3）用于产生指示对应于最后延迟定时信号的定时信号的部分周期的数量的信号的线包含特定特征的线。连接到隔离器的第一和第二计数器（5,8）被启用以连续的时间段被测量，并且分别连接到第一和第二计数器的第一和第二锁存器（11,12）在交替的连续时间结束时被锁存期间。连接到第一和第二锁存器的算术模块（22）获得它们的输出值之间的差值，该差分值分别表示连续的时间段。

8. 发明申请

WO0059113A9 PULSE CLOCK/SIGNAL DELAY APPARATUS AND METHOD 审中-公开
标题翻译：脉冲时钟/信号延迟装置和方法
公开(公告)号：WO0059113A9
公开(公告)日：2001-11-15
申请号：PCT/GB0001169
申请日：2000-03-27
申请人： ARKAS EVANGELOS , ARKAS NICHOLAS
发明人： ARKAS EVANGELOS , ARKAS NICHOLAS
IPC分类号： G06F1/10 , H03K5/13 , H03K5/15
CPC分类号： G06F1/10 , H03K5/131 , H03K5/133
摘要： A Pulse Clock Delay (PCD) apparatus (208) includes a selectable plurality (Nd) of series-connected pulse transition delay units (209) from a total plurality (Nmax) of such units. Each unit provides an incremental transition delay interval DELTA t. The PCD may be connected to a first intermediate proximal node (nla) and an adjacent electrically isolated second intermediate node (nlb) where the first and second intermediate nodes are in a shorter (215a, 215b) of two signal paths having respective proximal and spaced apart distal ends (212, 216) in an electrical network. Control means (205), responsive to the difference in electrical length between the two signal paths (214, 215), configures the switchable selection means to select a particular number of delay segments such that the propagation of a first edge transition (102) through the series combination of the shorter first path (215a, 215b) and the delay segment (208) is delayed sufficiently to arrive at the second path distal end (216) within +/- DELTA t of the time of arrival of the first edge transition propagating through the second path. Multiple PCDs may be distributed on a PCB to compensate delay differences for multiple pairs of unequal length bifurcated clock/signal lines.
摘要翻译：脉冲时钟延迟（PCD）装置（208）包括来自这些单元的总多个（Nmax）的可选择的多个（Nd）串联脉冲转移延迟单元（209）。每个单元提供递增的过渡延迟间隔DELTA t。 PCD可以连接到第一中间近端节点（nla）和相邻的电隔离的第二中间节点（nlb），其中第一和第二中间节点处于具有相应近端和间隔的两个信号路径的较短（215a，215b）在电网中的分开的远端（212,216）。控制装置（205）响应于两个信号路径（214,215）之间的电长度的差异，配置可切换选择装置来选择特定数量的延迟段，使得第一边缘过渡（102）的传播通过较短的第一路径（215a，215b）和延迟段（208）的串联组合被充分延迟以在第一边缘过渡的到达时间的+/- DELTA内到达第二路径远端（216）通过第二条路径传播。多个PCD可以分布在PCB上以补偿多对不等长度分支时钟/信号线的延迟差异。

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