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1. 发明申请

WO2020033816A1 CHANNEL SWITCHOVER POWER MULTIPLEXER CIRCUITS, AND METHODS OF OPERATING THE SAME 审中-公开
公开(公告)号：WO2020033816A1
公开(公告)日：2020-02-13
申请号：PCT/US2019/045884
申请日：2019-08-09
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： CHOI, Jae, Won , BECK, Sungho , TURKSON, Richard , KLARENBEEK, Johnny , LI, Bixia
IPC分类号： H03K5/14 , H03K17/00
摘要： An example power multiplexer (100) includes: a first transistor (105) coupled to a first input (102); a second transistor (106) coupled to the first transistor (105) to couple a first voltage at the first input (102) to an output (101); a third transistor coupled to a second input; a fourth transistor coupled to the third transistor to couple a second voltage at the second input to the output (101); a diode amplifier (142) to provide a third voltage to a gate (105C) of the first transistor (105) to block a reverse current; and a soft-start amplifier to provide a fourth voltage to a gate of the fourth transistor to turn on the fourth transistor with a constant ramp rate.

2. 发明申请

WO2019147556A1 INTEGRATED TRENCH CAPACITOR FORMED IN AN EPITAXIAL LAYER 审中-公开
公开(公告)号：WO2019147556A1
公开(公告)日：2019-08-01
申请号：PCT/US2019/014518
申请日：2019-01-22
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： LIN, He , JIA, Jiao , LIU, Yunlong , JAIN, Manoj
IPC分类号： H01L21/70 , H01L27/04 , H01L23/48
摘要： A trench capacitor (150) includes at least one epitaxial semiconductor surface layer (104a, 104b) on a semiconductor substrate (102) having a doping level that is less than a doping level of the semiconductor substrate (102). Trenches are formed through at least one half of a thickness of the epitaxial semiconductor surface layer (104a, 104b). The epitaxial semiconductor surface layer (104a, 104b) is thicker than a depth of the trenches. At least one capacitor dielectric layer (110) lines a surface of the trenches. At least one trench fill layer (112) on the dielectric layer (110) fills the trenches.

3. 发明申请

WO2018111918A1 METHODS AND SYSTEMS FOR ANALYZING IMAGES IN CONVOLUTIONAL NEURAL NETWORKS 审中-公开
公开(公告)号：WO2018111918A1
公开(公告)日：2018-06-21
申请号：PCT/US2017/065881
申请日：2017-12-12
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： MODY, Mihir, Narendra , MATHEW, Manu , GHONE, Chaitanya, Satish
IPC分类号： G06T7/262
摘要： A method (500) for analyzing images to generate output features includes receiving input features of the image and performing (502) Fourier transforms on each input feature. Kernels having coefficients of trained features are received and on-the-fly Fourier transforms (OTF-FTs) are performed (510) on the coefficients in the kernels. The output of each Fourier transform and each OTF-FT are multiplied together (512) to generate products, and each of the products are added (513) to produce one sum for each output feature. Two-dimensional inverse Fourier transforms are performed (516) on each sum.

4. 发明申请

WO2017173295A1 FAIL-SAFE FOR SHARED PIN 审中-公开
标题翻译：失去安全的共享密码
公开(公告)号：WO2017173295A1
公开(公告)日：2017-10-05
申请号：PCT/US2017/025418
申请日：2017-03-31
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： DUBEY, Sumit , AGARWAL, Nitin
IPC分类号： H03K3/00
CPC分类号： H02H3/20
摘要： In described examples, an integrated circuit IC (100A) provides an improved fail-safe signal (PKEEP2) to a module sharing a fail-safe pin at which a voltage can be greater than a voltage of an upper rail. The IC (100 A) includes: a first circuit segment (102, 104, 106) that receives a first fail-safe signal (PKEEP) and a first power-down signal (PWDN) and provides an intermediate signal (PWDNZ1), wherein the first fail-safe signal (PKEEP) indicates when the voltage at the fail-safe pin is greater than the upper rail, and the first power-down signal (PWDN) indicates when the module is powered down; and a second circuit segment (108, 110) connected to receive the intermediate signal (PWDNZ1) and to provide the improved fail-safe signal (PKEEP2) to the module.
摘要翻译：在所描述的示例中，集成电路IC（100A）向共享故障安全引脚的模块提供改进的故障安全信号（PKEEP2），在该模块处，电压可以大于上部导轨。 IC（100A）包括：接收第一故障安全信号（PKEEP）和第一断电信号（PWDN）并提供中间信号（PWDNZ1）的第一电路段（102,104,106），其中第一个故障安全信号（PKEEP）指示故障安全引脚上的电压何时大于上导轨，第一个掉电信号（PWDN）指示模块何时掉电; 和被连接以接收中间信号（PWDNZ1）并向模块提供改进的故障安全信号（PKEEP2）的第二电路段（108,110）。

5. 发明申请

WO2015157708A1 TRAY LOADING SYSTEM FOR ELECTRONIC COMPONENTS 审中-公开
标题翻译：电子元件托盘装载系统
公开(公告)号：WO2015157708A1
公开(公告)日：2015-10-15
申请号：PCT/US2015/025437
申请日：2015-04-10
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： RAMIREZ, JR., Daniel, Mendoza , NIEVA, Giovanni, Hufana , MACARANAS, Alvin Noel, M. , AQUINO, Brian, Sardoma
IPC分类号： H05K13/02
CPC分类号： G01R31/2893 , B07C5/3404
摘要： In described examples, a tray loading system (18) for tested electronic components (111, 113) includes a tray loading bin (36) adapted to prevent trays of a first configuration (20) from being operably received in a first bin operating mode and to operably receive trays of the first configuration (20) in a second bin operating mode. The system (18) also includes an operating mode switching assembly adapted to automatically change from the second operating mode to the first operating mode in response to an operation associated with removal of loaded trays of the first configuration (20) from the tray loading bin (36).
摘要翻译：在所描述的示例中，用于测试的电子部件（111,113）的托盘装载系统（18）包括托盘装载箱（36），其适于防止第一配置（20）的托盘在第一仓操作模式下被可操作地接收;以及以在第二仓操作模式中可操作地接收第一配置（20）的托盘。系统（18）还包括操作模式切换组件，其适于响应于从第二配置（20）从托盘加载仓移除装载的托盘（20）的相关操作而自动地从第二操作模式改变到第一操作模式 36）。

6. 发明申请

WO2019075026A1 INTERPOSER BETWEEN MICROELECTRONIC PACKAGE SUBSTRATE AND DIELECTRIC WAVEGUIDE CONNECTOR 审中-公开
公开(公告)号：WO2019075026A1
公开(公告)日：2019-04-18
申请号：PCT/US2018/055167
申请日：2018-10-10
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： HAROUN, Baher , HERBSOMMER, Juan, Alejandro , SCHUPPENER, Gerd , SANKARAN, Swaminathan
IPC分类号： H01P3/16 , H01R13/646
摘要： An interposer (110) that acts as a buffer zone between a transceiver IC (120) and a dielectric waveguide (131, 132) interconnect is used to establish two defined reference planes that can be optimized independently. The interposer (110) includes a block of material having a first interface region (113) to interface with an antenna (121, 122) coupled to an integrated circuit (123) and a second interface region (114) to interface to the dielectric waveguide (131, 132). An interface waveguide (111, 112) is formed by a defined region positioned within the block of material between the first interface region (113) and the second interface region (114).

7. 发明申请

WO2018136795A3 ETCHING PLATINUM-CONTAINING THIN FILM USING PROTECTIVE CAP LAYER 审中-公开
公开(公告)号：WO2018136795A3
公开(公告)日：2018-07-26
申请号：PCT/US2018/014522
申请日：2018-01-19
申请人： TAXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： MEIER, Sabastian , RINCK, Helmut , MITTELSTAEDT, Mike
IPC分类号： H01L21/311 , H01L21/469
摘要： A microelectronic device (200) is formed by forming a platinum-containing layer (220) on a substrate (202) of the microelectronic device (200). A cap layer (232) is formed on the platinum-containing layer (220) so that an interface between the cap layer (232) and the platinum-containing layer (220) is free of platinum oxide. The cap layer (232) is etchable in an etch solution which also etches the platinum-containing layer (220). The cap layer (232) may be formed on the platinum-containing layer (220) before platinum oxide forms on the platinum-containing layer (220). Alternatively, platinum oxide on the platinum-containing layer (220) may be removed before forming the cap layer (232). The platinum-containing layer (220) may be used to form platinum silicide (226). The platinum-containing layer (220) may be patterned by forming a hard mask or masking platinum oxide (264) on a portion of the top surface of the platinum-containing layer (220) to block the wet etchant.

8. 发明申请

WO2017185065A1 SINTERED METAL FLIP CHIP JOINTS 审中-公开
标题翻译：烧结金属倒装片接头
公开(公告)号：WO2017185065A1
公开(公告)日：2017-10-26
申请号：PCT/US2017/029000
申请日：2017-04-21
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： WACHTLER, Kurt, Peter , CHAE, Seunghyun , COOK, Benjamin, Stassen
IPC分类号： H01L23/495 , H01L23/50 , B22F3/10 , B82Y30/00 , B33Y80/00
摘要： In described examples, an integrated circuit die is fabricating to have multiple contacts. A metal post (204) is formed on each contact (207). A bump (212) is formed on a contact region (221) of a leadframe (220) or on the post (204). The bump (212) is formed with a material that includes metal nanoparticles. The integrated circuit die is attached to the leadframe (220) by aligning the metal post (204) to the leadframe (220) and sintering the metal nanoparticles in the bump (212) to form a sintered metal bond between the post (204) and corresponding contact region (221) of the leadframe (220).
摘要翻译：在所描述的示例中，集成电路管芯正在制造以具有多个触点。金属柱（204）形成在每个触点（207）上。凸块（212）形成在引线框（220）的接触区域（221）上或柱（204）上。凸块（212）由包括金属纳米颗粒的材料形成。通过使金属柱（204）与引线框（220）对准并烧结凸块（212）中的金属纳米颗粒以在柱（204）与柱（220）之间形成烧结金属结合，将集成电路管芯附接到引线框引线框架（220）的相应接触区域（221）。

9. 发明申请

WO2017139808A1 PULSE-SHAPING AMPLIFIER SYSTEM 审中-公开
标题翻译：脉冲整形放大器系统
公开(公告)号：WO2017139808A1
公开(公告)日：2017-08-17
申请号：PCT/US2017/017744
申请日：2017-02-13
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： EASWARAN, Sri, Navaneethakrishnan
IPC分类号： H03F3/04 , H03F3/20 , H03G11/08
CPC分类号： H04B1/40 , H03F1/0227 , H03F3/193 , H03F3/245 , H03F3/301 , H03F2200/18 , H03F2200/249 , H03F2200/451 , H04L67/12
摘要： In described examples, an amplifier system (10) includes an input stage (12) configured to receive an input pulse signal and to generate a reference voltage pulse based on the input pulse signal. The amplifier system (10) also includes an amplifier stage (14) that receives at least one power voltage and is configured to amplify the reference voltage pulse and to provide pulse-shaping of the amplified reference voltage pulse based on a change of amplitude of the at least one power voltage resulting from an amplitude of the reference voltage pulse.
摘要翻译：在所描述的示例中，放大器系统（10）包括被配置为接收输入脉冲信号并且基于输入脉冲信号生成参考电压脉冲的输入级（12）。放大器系统（10）还包括放大器级（14），其接收至少一个电源电压并且被配置为放大参考电压脉冲并且基于放大器系统（10）的振幅的变化来提供放大的参考电压脉冲的脉冲整形至少一个由参考电压脉冲的振幅产生的电源电压。

10. 发明申请

WO2016126989A1 SPECTROGRAPHIC MATERIAL ANALYSIS USING MULTI-FREQUENCY INDUCTIVE SENSING 审中-公开
标题翻译：使用多频感应感测的光谱材料分析
公开(公告)号：WO2016126989A1
公开(公告)日：2016-08-11
申请号：PCT/US2016/016638
申请日：2016-02-04
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS JAPAN LIMITED
发明人： REITSMA, George, Pieter
IPC分类号： G01N27/90 , G01R27/00
CPC分类号： G01N33/483 , A61B5/053 , A61B5/0531
摘要： In described examples, a multi-frequency inductive sensing system (10) can be used for spectrographic material analysis of a conductive target material (30) based on electrical impedance spectroscopy. An inductive senor (14) can be driven with an excitation current at multiple sensor excitation frequencies (ω) to project a time-varying magnetic field (16) into a sensing area (19) on the surface (31) of the target material, inducing eddy currents within the target material. The inductive sensor can be characterized by a sensor impedance Z(ω) as a function of the sensor excitation frequency (ω) and the resulting induced eddy currents. Multiple sensor impedance Zs(ω) measurements at the multiple sensor excitation frequencies (ω) can be determined, which represent electromagnetic properties of the target material (such as permittivity ε, permeability μ, and resistivity ρ), based on the induced eddy currents. The multiple sensor excitation frequencies (ω) and corresponding multiple sensor impedance Zs(ω) measurements can be selected for particular target penetration depths (t).
摘要翻译：在所描述的示例中，多频感应感测系统（10）可用于基于电阻抗谱的导电靶材料（30）的光谱材料分析。感应传感器（14）可以以多个传感器激励频率（ω）的激励电流驱动，以将时变磁场（16）投射到目标材料的表面（31）上的感测区域（19）中，在目标材料内引起涡流。感应传感器的特征可以在于传感器阻抗Z（ω）与传感器激励频率（ω）和所产生的感应涡流有关。可以基于感应的涡流来确定在多个传感器激励频率（ω）下的多传感器阻抗Zs（ω）测量，其表示目标材料的电磁特性（例如介电常数ε，磁导率μ和电阻率ρ）。可以为特定的目标穿透深度（t）选择多个传感器激励频率（ω）和相应的多传感器阻抗Zs（ω）测量值。

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