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1. 发明申请

WO1991007015A1 PROGRAMMABLE LOGIC CELL AND ARRAY 审中-公开
标题翻译：可编程逻辑单元和阵列
公开(公告)号：WO1991007015A1
公开(公告)日：1991-05-16
申请号：PCT/US1990006108
申请日：1990-10-24
申请人： CONCURRENT LOGIC, INC.
发明人： CONCURRENT LOGIC, INC. , FURTEX, Frederick, C.
IPC分类号： H03K19/173
CPC分类号： G06F17/5054 , H03K19/17704 , H03K19/17728
摘要： A logic cell (20) is described having four inputs (22a, 22b, 23a, 23b) outputs (24a, 24b, 25a, 25b), a control store (32), means (34, 35) for multiplexing the four inputs onto two leads (44a, 44b) and logic means (38) that operate in response to the signals on the two leads (44a, 44b) and signals from the control store (32) to produce output signals which are applied to the four outputs. Illustrative logic functions provided by the logic means (38) include a cross-over or identity function, a change in routing direction of an input signal, NAND and XOR gates and a D-type flip-flop. The selection of two of the four inputs as well as the selection of the particular logic function that is implemented is controlled by control bits stored in the control store (32). Numerous such logic cells (20) are arranged in a two-dimensional matrix such that each cell has four nearest neighbor cells, one to its left (or to the West) one to its right (or to the East), one above it (or to the North) and one below it (or to the South). Each one of the four inputs (22a, 22b, 23a, 23b) to a logic cell comes from a different one of that cell's four nearest neighbors and similary each one of a cell's outputs (24a, 24b, 25a, 25b) is provided to a different one of that cell's four nearest neighbors. As a result of this arrangement, individual cells can be combined to produce blocks of cells that implement all manner of functions.
摘要翻译：描述了具有四个输入（22a，22b，23a，23b）输出（24a，24b，25a，25b），控制存储器（32），用于将四个输入复用到两个引线（44a，44b）和逻辑装置（38），其响应于两个引线（44a，44b）上的信号和来自控制存储器（32）的信号而工作，以产生施加到四个输出端的输出信号。由逻辑装置（38）提供的说明性逻辑功能包括交叉或识别功能，输入信号的路由方向的变化，NAND和XOR门和D型触发器。四个输入中的两个的选择以及所实现的特定逻辑功能的选择由存储在控制存储器（32）中的控制位来控制。许多这样的逻辑单元（20）被布置在二维矩阵中，使得每个单元具有四个最近相邻单元，一个在其左侧（或向西）一个在其右侧（或向东），一个位于其上方或北部）和其下一个（或南部）。到逻辑单元的四个输入（22a，22b，23a，23b）中的每一个来自该单元的四个最近邻的不同的一个，并且单元的输出（24a，24b，25a，25b）中的每一个被提供给该小区的四个最近邻居中的另一个。作为这种安排的结果，可以将各个单元组合以产生实现各种功能的单元格块。

2. 发明申请

WO1992008286A1 PROGRAMMABLE LOGIC CELL AND ARRAY 审中-公开
标题翻译：可编程逻辑单元和阵列
公开(公告)号：WO1992008286A1
公开(公告)日：1992-05-14
申请号：PCT/US1991008095
申请日：1991-11-01
申请人： CONCURRENT LOGIC, INC.
发明人： CONCURRENT LOGIC, INC. , CAMAROTA, Rafael, C. , FURTEK, Frederick, C. , HO, Walford, W. , BROWDER, Edward, H.
IPC分类号： H03K19/177
CPC分类号： H03K19/17728 , H03K19/17704
摘要： A programmable logic array (10) comprising cells (22) and a bus network (12) in which the cells are arranged in a two-dimensional matrix of rows and columns and are interconnected by the bus network (12). The cells (22) are also interconnected by a two-dimensional array of direct connections between a cell (22) and its four nearest neighbors, one to its left (or to the West), one to its right (or to the East), one above it (or to the North) and one below it (or to the South). Each cell (22) comprises eight inputs, eiht outputs, means for multiplexing the eight inputs onto two leads and logic means that operate in response to the signals on the two leads to produce output signals which are applied to the eight outputs. The bus network (12) comprises a local (25), a turning (26) and an express bus (27) for each row and column of the array (10) and repeater means (24) for partitioning said buses of a given row or column so as to form bus segments. The bus network (12) provides for transfer of data to the cells (22) of the array (10) without using the cells (22) as individual wires.

3. 发明申请

WO1989003138A1 PROGRAMMABLE, ASYNCHRONOUS LOGIC CELL AND ARRAY 审中-公开
标题翻译：可编程，异步逻辑单元和阵列
公开(公告)号：WO1989003138A1
公开(公告)日：1989-04-06
申请号：PCT/US1987002392
申请日：1987-09-23
申请人： CONCURRENT LOGIC, INC.
发明人： CONCURRENT LOGIC, INC. , FURTEK, Frederick, C.
IPC分类号： H03K19/177
CPC分类号： H03K19/17704 , G06F17/5013 , G11C29/006 , H03K19/17728 , H03K19/17736 , H03K19/1774
摘要： An asynchronous logic cell (42) and a two- or three-dimensional array (40) formed of such cells. Each cell comprises a number of exclusive-OR gates (12'), Muller C-elements (20') and programmable switches (30 or 32). The logic cell is reprogrammable and may even be reprogrammed dynamically, such as to perform recursive operations or simply to make use of hardware which is temporarily idle. Programming is accomplished by setting the states of the switches in each cell. A user-friendly programming environment facilitates the programming of the switches. The array can be used to implement any circuit capable of being modelled as a broad class of Petri Nets. Configurations for (i.e., programs for setting cell switches to create) circuit blocks such as adders, multiplexers, buffer stacks, and so forth, may be stored in a library for future reference. With an adequate library, custom hardware can be designed by simply mapping stored blocks onto chips and connecting them together. Further, because the array is regular and switch settings can produce logical wires, crossovers, connections and routings running both ''horizontally'' and ''vertically'', it is in general possible to ''wire around'' defective elements. If a large wafer contains defective cells, those cells can simply be avoided and bypassed, with the remainder of the wafer remaining useful.
摘要翻译：由这样的单元形成的异步逻辑单元（42）和二维或三维阵列（40）。每个单元包括多个异或门（12'），穆勒C元件（20'）和可编程开关（30或32）。逻辑单元是可重新编程的，并且甚至可以动态地重新编程，例如执行递归操作或简单地利用暂时空闲的硬件。通过设置每个单元中开关的状态来完成编程。用户友好的编程环境有助于开关的编程。该阵列可用于实现能够被建模为广泛类型Petri网的任何电路。诸如加法器，多路复用器，缓冲器堆栈等的电路块（即，用于设置单元开关的程序）的配置可以存储在库中以供将来参考。使用足够的库，可以通过简单地将存储的块映射到芯片并将它们连接在一起来设计定制硬件。此外，由于阵列是规则的，开关设置可以产生“水平”和“垂直”两种运行的逻辑导线，交叉，连接和布线，通常可能“绕线”有缺陷的元件。如果大晶片含有有缺陷的电池，则可以简单地避免和旁路这些电池，剩余的晶片仍然有用。

4. 发明申请

WO1993005577A1 PROGRAMME LOGIC CELL AND ARRAY 审中-公开
标题翻译：程序逻辑单元和阵列
公开(公告)号：WO1993005577A1
公开(公告)日：1993-03-18
申请号：PCT/US1992007376
申请日：1992-08-28
申请人： CONCURRENT LOGIC, INC.
发明人： CONCURRENT LOGIC, INC. , FURTEK, Frederick, C. , CAMAROTA, Rafael, C.
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/17704 , H03K19/17728
摘要： An improved programmable logic cell (1) for use in a programmable logic array comprising cells which are arranged in two-dimensional matrix of rows and columns and are interconnected by a two-dimensional array of direct connections between a cell (1) and its four nearest neighbors, one to its left (or to the West) (3a, 3b, 7a, 7b) and one to its right (or to the East) (5a, 5b, 9a, 9b), one above it (or to the North) (2a, 2b, 6a, 6b) and one below it (or to the South) (4a, 4b, 8a, 8b). Each cell receives input (s) from each of its nearest neighbors and additional input(s) from a bus, pin, or neighbor and may be programmed to generate a variety of logical functions at its outputs which connect to the cell's four nearest neighbors. The core of the improved logic cell (fig.2) comprises two upstream gates (21, 23) the outputs of which feed two downstream gates (28, 41), one of which is an exclusive-OR gate (28) which feeds a downstream register (33). Additional programmable connections and other logic augment the cell core to produce cell embodiments which can be configured to efficiently implement various logical functions. Among the functions which may be implemented by the improved cell are a number of two-level combinational functions (such as multiplexing) and sequential functions (such as counting and shifting). A variety of cell embodiments based on the improved cell core are illustrated.
摘要翻译：一种用于可编程逻辑阵列的改进的可编程逻辑单元（1），包括以行和列的二维矩阵排列并且通过在单元（1）与其四个单元之间的直接连接的二维阵列互连的单元最近的邻居，一个在左边（或西部）（3a，3b，7a，7b），一个在右边（或东边）（5a，5b，9a，9b），一个在它上面（或到北）（2a，2b，6a，6b）和其下一个（或南部）（4a，4b，8a，8b）。每个小区从其最近的邻居中的每一个接收输入，并从总线，引脚或邻居接收输入，并且可以被编程为在连接到小区的四个最近邻居的输出处生成各种逻辑功能。改进的逻辑单元（图2）的核心包括两个上游门（21,23），其输出端馈送两个下游门（28,41），其中一个是异或门（28），其馈送下游寄存器（33）。附加的可编程连接和其它逻辑增加了单元核心以产生可被配置为有效地实现各种逻辑功能的单元实施例。可以由改进的小区实现的功能之一是两级组合功能（如复用）和顺序功能（如计数和移位）的数量。示出了基于改进的单元芯的各种单元实施例。

5. 发明申请

WO1988003727A1 PROGRAMMABLE LOGIC CELL AND ARRAY 审中-公开
标题翻译：可编程逻辑单元和阵列
公开(公告)号：WO1988003727A1
公开(公告)日：1988-05-19
申请号：PCT/US1987002912
申请日：1987-11-04
申请人： CONCURRENT LOGIC, INC.
发明人： CONCURRENT LOGIC, INC. , FURTEK, Frederick, C.
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , G06F17/5054 , H03K19/17704 , H03K19/17728 , H03K19/17796
摘要： Programmable logic cells, and arrays of those cells, having certain characteristics, including: (1) the ability to program each cell to act either as a logic element or as a logical identity element(s) between one or more inputs and one or more outputs; (2) the ability to rotate circuits by 90° and to reflect circuits about horizontal and vertical axes; (3) an integrated logic and communication structure which emphasizes strictly local communications; (4) simple logic functions available at the cell level, making available a very fine-grained logic structure; and (5) suitability for implementation of both synchronous and asynchronous logic, including speed-independent circuits. Cells are arranged in a grid, with each cell communicating with its north, east, west and south neighbors. The cells are programmable to several states. Using a graphics-based programming environment, the user may construct systems at a pictorial block diagram level, rather than having to be concerned about the detailed implementation of the internal structure of each block. Blocks may be rotated and they may be reflected about horizontal and vertical axes, to place their input and output connections on different sides and positions without altering the internal electrical operation of the blocks.

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