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71. 发明申请

WO1993008526A1 CROSS COUPLING MECHANISMS FOR MICROPROCESSOR INSTRUCTIONS USING PIPELINING SYSTEMS 审中-公开
标题翻译：使用管道系统的微处理器指令的交叉耦合机制
公开(公告)号：WO1993008526A1
公开(公告)日：1993-04-29
申请号：PCT/US1992008650
申请日：1992-10-12
申请人： INTEL CORPORATION
发明人： INTEL CORPORATION , HAMMOND, Gary, N.
IPC分类号： G06F09/38
CPC分类号： G06F9/3867 , G06F9/3836 , G06F9/3838 , G06F9/3857 , G06F9/3885
摘要： Apparatus and methods for expediting the completion of microprocessor instructions using a microprocessor pipelining system is disclosed. According to the present invention two or more dependent instructions processed through two or more microprocessor pipelines are simultaneously completed. This simultaneous completion of the two or more dependent instructions is achieved by the use of various embodiments of the present invention's Advanced Cross Coupler which operates as a link between a number of pipelines.

72. 发明申请

WO1993001552A1 ASYNCHRONOUS MODULAR BUS ARCHITECTURE WITH BURST CAPABILITY 审中-公开
标题翻译：具有爆发能力的异步模块化总线架构
公开(公告)号：WO1993001552A1
公开(公告)日：1993-01-21
申请号：PCT/US1992005482
申请日：1992-06-30
申请人： INTEL CORPORATION
发明人： INTEL CORPORATION , PAWLOWSKI, Stephen, Scott , MACWILLIAMS, Peter, Dalton , KOLINKSKI, Jerzy, Bogdan
IPC分类号： G06F13/32
CPC分类号： G06F13/28 , G06F12/0831 , G06F12/0879 , G06F13/32
摘要： An asynchronous computer bus (120) providing transfers of data on consecutive processor clock cycles. The bus comprising consecutive data transfer commence indication means (620, 630), starting address transmission means (401, 501), consecutive data transfer indication means (506, 606), and data transmission means (120). The invention provides for the ''burst'' capabilities of modern processors wherein entire blocks of data are transmitted within a single request.

73. 发明申请

WO1992022035A1 CACHE SUBSYSTEM FOR MICROPROCESSOR BASED COMPUTER WITH ASYNCHRONOUS AND SYNCHRONOUS DATA PATH 审中-公开
标题翻译：基于微处理器的计算机的缓存子系统具有异步和同步数据路径
公开(公告)号：WO1992022035A1
公开(公告)日：1992-12-10
申请号：PCT/US1992004744
申请日：1992-06-04
申请人： INTEL CORPORATION
发明人： INTEL CORPORATION , MACWILLIAMS, Peter, D. , WEBB, Clair, C. , FARRELL, Robert, L.
IPC分类号： G06F13/00
CPC分类号： G06F12/0864 , G06F12/0804 , G06F12/0835 , G06F12/0862 , G06F12/0897 , G06F2212/6082
摘要： An integrated circuit which implements a cache SRAM storage element (13) is disclosed which includes a CPU bus (14) interface incorporating mux/buffer circuits (20) for optimizing burst read and write operations across the CPU bus (14). Theses circuits allow a full cache line to be read/written in a single access of the SRAM array (22). Control logic is utilized within the CPU (10). The memory bus interface includes internal buffers (40, 41, 45, 46) used in performing memory bus reads, write-throughs, write-backs and snoops. Tracking logic is employed for determining the appropriate internal buffer to be utilized for a particular memory bus cycle. Additionally, a data path is included for transparency passing data between the CPU (10) and memory bus interfaces without disturbance of the SRAM array (22).

74. 发明申请

WO2014158206A1 HYBRID BEAMFORMING FOR DATA TRANSMISSION 审中-公开
标题翻译：用于数据传输的混合波束形成
公开(公告)号：WO2014158206A1
公开(公告)日：2014-10-02
申请号：PCT/US2013/048008
申请日：2013-06-26
申请人： INTEL CORPORATION , SHIRANI-MEHR, Hooman , SAJADIEH, Masoud
发明人： INTEL CORPORATION , SHIRANI-MEHR, Hooman , SAJADIEH, Masoud
IPC分类号： H04W24/00 , H04W16/28
CPC分类号： H04W8/082 , H04B1/56 , H04B7/0417 , H04B7/0452 , H04B7/0619 , H04B7/063 , H04B7/0695 , H04B7/088 , H04L1/1864 , H04L5/0007 , H04L5/0048 , H04L5/0051 , H04L5/0057 , H04L5/0085 , H04L25/0206 , H04L25/03305 , H04L47/803 , H04L65/4092 , H04L65/601 , H04L65/602 , H04L65/604 , H04L65/607 , H04L65/608 , H04L65/80 , H04L2025/03426 , H04M1/72572 , H04N21/2402 , H04N21/8456 , H04N21/8543 , H04W4/021 , H04W8/02 , H04W8/06 , H04W24/00 , H04W24/02 , H04W28/02 , H04W28/0226 , H04W28/0289 , H04W28/085 , H04W28/20 , H04W36/0005 , H04W36/0011 , H04W36/0022 , H04W36/08 , H04W36/22 , H04W36/26 , H04W36/30 , H04W48/06 , H04W48/12 , H04W48/16 , H04W48/18 , H04W56/001 , H04W72/0446 , H04W72/046 , H04W72/082 , H04W76/15 , H04W84/042 , H04W84/045 , H04W84/12 , H04W88/02 , H04W88/08 , H04W88/10 , Y02D70/00 , Y02D70/1224 , Y02D70/1242 , Y02D70/1244 , Y02D70/1246 , Y02D70/1262 , Y02D70/1264 , Y02D70/142 , Y02D70/144 , Y02D70/146 , Y02D70/162 , Y02D70/164 , Y02D70/168 , Y02D70/21 , Y02D70/23 , Y02D70/444
摘要： Technology to provide hybrid beamforming feedback is disclosed. In an example, a user equipment (UE) can include computer circuitry configured to: Receive a reference signal (RS) from a node; calculate an optimal channel direction from the RS; calculate an optimal signal-to-interference-plus-noise ratio (SINR) for the optimal channel direction, where the optimal SINR is conditionally calculated with an intra-cell interference component or calculated without the intra-cell interference component based on a feedback configuration; and transmit the optimal channel direction and the optimal SINR to the node.
摘要翻译：公开了提供混合波束成形反馈的技术。在一个示例中，用户设备（UE）可以包括被配置为：从节点接收参考信号（RS）的计算机电路; 从RS计算最佳信道方向; 计算最佳信道方向的最佳信号与干扰加噪声比（SINR），其中最佳SINR有条件地用小区内干扰分量计算，或者基于反馈配置计算而不具有小区内干扰分量 ; 并向节点发送最优信道方向和最佳SINR。

75. 发明申请

WO1999009737A1 COLOR CHANNEL INDEPENDENT ELECTRONIC SHUTTER FOR SOLID STATE IMAGE SENSOR 审中-公开
标题翻译：用于固态图像传感器的彩色通道独立电子快门
公开(公告)号：WO1999009737A1
公开(公告)日：1999-02-25
申请号：PCT/US1997021557
申请日：1997-11-25
申请人： INTEL CORPORATION
发明人： INTEL CORPORATION , SEVERIN, Warren , METZ, Werner
IPC分类号： H04N05/30
CPC分类号： H04N5/3537 , H04N9/045
摘要： An improved color image sensor (100) semiconductor integrated circuit (IC) where photosites (111-124) of a particular color receive an independent electronic shutter control (300) signal which allows the exposure time of pixels corresponding to each color to be set independently. The embodiments aim to improve image quality under lower illumination conditions by improving signal-to-noise ratio in the color channels having lower illumination, and permit some manufacturing variation in the sensor IC, in the Color Filter Array (CFA), and in the optical component manufacturing processes. The invention may be particularly useful in portable digital image capture systems, such as the digital camera, but may also find use in color scanners and certain color copiers.
摘要翻译：一种改进的彩色图像传感器（100）半导体集成电路（IC），其中特定颜色的光斑（111-124）接收独立的电子快门控制（300）信号，其允许独立地设置与每种颜色对应的像素的曝光时间。这些实施例旨在通过改善具有较低照度的彩色通道中的信噪比来改善较低照明条件下的图像质量，并且允许在滤色器阵列（CFA）中和传感器IC中的传感器IC中的一些制造变化。组件制造过程。本发明可以在诸如数字照相机的便携式数字图像捕获系统中特别有用，但是也可以用于彩色扫描仪和某些彩色复印机。

76. 发明申请

WO1998034403A1 APPARATUS AND METHOD FOR SECURING CAPTURED DATA TRANSMITTED BETWEEN TWO SOURCES 审中-公开
标题翻译：用于保护两个源之间传输的捕获数据的装置和方法
公开(公告)号：WO1998034403A1
公开(公告)日：1998-08-06
申请号：PCT/US1997000958
申请日：1997-01-30
申请人： INTEL CORPORATION , DAVIS, Derek, L. , JONES, Peter
发明人： INTEL CORPORATION
IPC分类号： H04N07/167
CPC分类号： H04L9/3263 , H04L9/3236 , H04L9/3247 , H04L2209/30 , H04L2209/38 , H04L2209/805
摘要： Implemented preferably within a video camera, a secure data capture device is used to prevent a captured data clip (315) from being fraudulently altered without detection. The secure data capture device performs "time-bracketing" and/or "sequence ordering" operations to preserve data integrity through implementation of two registers incorporating a "State of the Universe" ("SOTO") number anda "sequence" number, respectively. Time bracketing is performed by digitally signing (310) a running hash (320) value representing the data clip appended to the SOTU number before the digital signature is "time-stamped". Sequence ordering is performed by digitally signing the digest (330) of the data frame or multiple data frames along with the sequence number.
摘要翻译：优选地在摄像机内部实现安全数据捕获装置，以防止被捕获的数据剪辑（315）在没有被检测的情况下被欺骗地改变。安全数据采集装置执行“时间包围”和/或“序列排序”操作，以分别通过实施包含“宇宙状态”（“SOTO”）号和“序列”号的两个寄存器来保持数据完整性。在数字签名被“加时间”之前，通过数字签名（310）表示附加到SOTU号码的数据剪辑的运行的散列（320）值来执行时间包围。通过对数据帧的摘要（330）或多个数据帧与序列号进行数字签名来执行序列排序。

77. 发明申请

WO1998033293A1 APPARATUS AND METHOD FOR PREVENTING DISCLOSURE THROUGH USER-AUTHENTICATION AT A PRINTING NODE 审中-公开
标题翻译：用于在打印节点上通过用户认证来防止泄露的装置和方法
公开(公告)号：WO1998033293A1
公开(公告)日：1998-07-30
申请号：PCT/US1997001190
申请日：1997-01-24
申请人： INTEL CORPORATION , DAVIS, Derek, L. , SMITH, Lionel
发明人： INTEL CORPORATION
IPC分类号： H04L09/00
CPC分类号： B41J29/54 , G06F21/608 , G06K15/005 , G06K15/02 , G06K15/1803 , H04L9/321 , H04L9/3226 , H04L9/3234 , H04L9/3263 , H04L63/0442 , H04L63/08 , H04L63/104 , H04N1/00838 , H04N1/4413 , H04N1/444 , H04N1/4486
摘要： A system (100) and method for preventing a copy of a document to the output from a printing node (130) until the printing node (130) authenticates the intended recipient. The system (100) includes the sending node (110), the printing node (130), and a communication link (120) coupling these nodes (110, 130) together in a network fashion. The sending node (110) has access to a public key (210) of the printing node (130) and uses this public key (210) to encrypt a header (265) and document (255) before transmission to the printing node (130) over the communication link (120). The printing node (130) has access to its private key (211) to decrypt the header (265) to ascertain whether the document (255) requires authentication by the intended recipient before being output.
摘要翻译：一种用于防止从打印节点（130）输出的文档的副本直到打印节点（130）认证预期接收者的系统（100）和方法。系统（100）包括发送节点（110），打印节点（130）以及以网络方式将这些节点（110,130）耦合在一起的通信链路（120）。发送节点（110）可以访问打印节点（130）的公开密钥（210），并且在传输到打印节点（130）之前使用该公开密钥（210）加密报头（265）和文档（255））通过通信链路（120）。打印节点（130）可以访问其专用密钥（211）来解密报头（265），以确定文档（255）在输出之前是否需要预期的接收方进行认证。

78. 发明申请

WO1998029951A1 METHOD AND APPARATUS FOR LOW POWER DATA TRANSMISSION 审中-公开
标题翻译：低功率数据传输的方法和装置
公开(公告)号：WO1998029951A1
公开(公告)日：1998-07-09
申请号：PCT/US1997023939
申请日：1997-12-18
申请人： INTEL CORPORATION
发明人： INTEL CORPORATION , STAMOULIS, Georgios, I. , SUGISAWA, Junji , ZHANG, Michael, Y.
IPC分类号： H03K19/0948
CPC分类号： H03K17/6872
摘要： A low power data transmission circuit includes a pass gate (20) having parallel connected n and p-channel CMOS transistors that transmit input data (DATA). To reduce power in a first embodiment, a circuit (28) disables the parallel-connected p-channel pass gate transistor except when the input data is high (logical 1). The p-channel pass gate transistor is needed to pass logical 1's without degradation. In the first embodiment, the n-channel pass gate transistor is enabled to transmit the input data on every clock cycle (CLOCK). In a second embodiment, the circuit (30) disables the parallel-connected n-channel transistor except when the input data is low (logical 0). The n-channel pass gate transistor is needed to pass logical 0's without degradation. In this embodiment, the p-channel pass gate transistor is enabled to transmit the input data on every clock cycle. These transmission circuits achieve substantial power savings by avoiding unnecessary charging and discharging of the pass gate transistors' gate capacitance on every clock cycle.
摘要翻译：低功率数据传输电路包括传输输入数据（DATA）的并行连接的n沟道CMOS晶体管和p沟道CMOS晶体管的栅极（20）。为了在第一实施例中降低功率，除了输入数据高（逻辑1）之外，电路（28）禁用并联p沟道栅极晶体管。需要p沟道栅极晶体管来使逻辑1不劣化。在第一实施例中，n通道栅极晶体管能够在每个时钟周期（CLOCK）上传输输入数据。在第二实施例中，除输入数据为低（逻辑0）之外，电路（30）禁止并联n沟道晶体管。需要n沟道栅极晶体管来使逻辑0无劣化。在本实施例中，p沟道栅极晶体管能够在每个时钟周期上传输输入数据。这些传输电路通过在每个时钟周期避免不必要的通过栅极晶体管栅极电容的充电和放电来实现实质的功率节省。

79. 发明申请

WO1998029875A1 A METHOD AND APPARATUS FOR BIT CELL GROUND CHOKING FOR IMPROVED MEMORY WRITE MARGIN 审中-公开
标题翻译：用于改进存储器写字符的位数字地址检测的方法和装置
公开(公告)号：WO1998029875A1
公开(公告)日：1998-07-09
申请号：PCT/US1997023214
申请日：1997-12-11
申请人： INTEL CORPORATION
发明人： INTEL CORPORATION , GREASON, Jeffrey, K.
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： A method and apparatus to increase the size of the design window for write margin and read stability margin of memory cells without requiring a voltage above the power supply voltage or below ground. An SRAM (300) consisting of an SRAM cell (320) having a ground reference (V. sub. GND) and a circuit (340) coupled to receive a first signal (T. sub. STRONG) and coupled to drive the ground reference. The circuit is configured to drive the ground reference to a first voltage if the first signal is in a first state. The circuit is configured such that the first node is at a second voltage if the first signal is in a second state, the first signal being in the first state indicating a write operation, the first signal being in the second state indicating a non-write operation, the first voltage being greater than the second voltage.
摘要翻译：一种增加存储器单元的写入余量和读取稳定裕度的设计窗口的大小的方法和装置，而不需要高于电源电压或低于地电压的电压。由具有接地基准（V. sub.NDC）的SRAM单元（320）和耦合以接收第一信号（T. sub.STRONG）的电路（340）组成的SRAM（300），并耦合以驱动地面基准。如果第一信号处于第一状态，该电路被配置为将接地参考电压驱动到第一电压。电路被配置为使得如果第一信号处于第二状态，则第一节点处于第二电压，第一信号处于第一状态，指示写入操作，第一信号处于第二状态，指示非写入第一电压大于第二电压。

80. 发明申请

WO1998029811A1 TIME-DISTRIBUTED ECC SCRUBBING TO CORRECT MEMORY ERRORS 审中-公开
标题翻译：分时纠错ECC纠错纠正内存错误
公开(公告)号：WO1998029811A1
公开(公告)日：1998-07-09
申请号：PCT/US1997021904
申请日：1997-11-24
申请人： INTEL CORPORATION
发明人： INTEL CORPORATION , HAYEK, George, R. , VENKATARAMAN, Radhakrishnan , AJANOVIC, Jasmin
IPC分类号： G06F11/08
CPC分类号： G06F11/106 , G06F11/1028 , G06F11/1052 , G11C29/52 , G11C2029/0409
摘要： Error correction circuitry (101) attempts to detect and correct, on-the-fly, erroneous words from RAM (102) within a computer system. Correctable errors are scrubbed without delaying the memory access cycle. The address of the section or row of RAM containing the correctable error is latched (130) for later use by a firmware-implemented interrupt-driven scrub routine (104) that reads and rewrites each word within the indicated memory section, resulting in the erroneous word being corrected on-the-fly and rewritten correctly. If the memory section size exceeds a threshold, the scrub process is divided into smaller subprocesses that are distributed in time using a delayed interrupt mechanism. Subprocess duration is kept short enough to avoid impairing the computer system response time. System management interrupts (120) and firmware (104) make the scrub routine independent of and transparent to the operating systems that may be run on the computer system.
摘要翻译：错误校正电路（101）尝试从计算机系统内的RAM（102）中检测并纠正错误的单词。擦除可纠正的错误，而不会延迟内存访问周期。锁存包含可纠正错误的RAM的部分或一行的地址（130），供以后使用的固件实现的中断驱动擦除程序（104）读取并重写所指示的存储器部分中的每个字，导致错误字被正确地修正并被正确地重写。如果存储器部分大小超过阈值，则擦除处理被划分为使用延迟中断机制在时间上分布的更小的子处理。子过程持续时间保持足够短以避免损害计算机系统响应时间。系统管理中断（120）和固件（104）使擦洗程序独立于可能在计算机系统上运行的操作系统并且是透明的。

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