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61. 发明申请

WO2013052056A1 APPARATUS AND METHOD FOR DYNAMICALLY MANAGING MEMORY ACCESS BANDWIDTH IN MULTI-CORE PROCESSOR 审中-公开
标题翻译：用于在多核处理器中动态地管理存储器访问带宽的装置和方法
公开(公告)号：WO2013052056A1
公开(公告)日：2013-04-11
申请号：PCT/US2011/055122
申请日：2011-10-06
申请人： INTEL CORPORATION , GENDLER, Alexander , NOVAKOVSKY, Larisa , LEIFMAN, George , RIP, Dana
发明人： GENDLER, Alexander , NOVAKOVSKY, Larisa , LEIFMAN, George , RIP, Dana
IPC分类号： G06F1/00 , G06F12/00 , G06F9/06
CPC分类号： G06F9/3802 , G06F12/0862
摘要： An apparatus and method are described for performing history-based prefetching. For example a method according to one embodiment comprises: determining if a previous access signature exists in memory for a memory page associated with a current stream; if the previous access signature exists, reading the previous access signature from memory; and issuing prefetch operations using the previous access signature.
摘要翻译：描述了用于执行基于历史的预取的装置和方法。例如，根据一个实施例的方法包括：确定存储器中是否存在与当前流相关联的存储器页面的先前访问签名; 如果存在先前的访问签名，则从存储器读取先前的访问签名; 并使用先前的访问签名发出预取操作。

62. 发明申请

WO2013048503A1 APPARATUS AND METHOD FOR IMPLEMENTING A MULTI-LEVEL MEMORY HIERARCHY HAVING DIFFERENT OPERATING MODES 审中-公开
标题翻译：用于实现具有不同操作模式的多级记忆层次的装置和方法
公开(公告)号：WO2013048503A1
公开(公告)日：2013-04-04
申请号：PCT/US2011/054444
申请日：2011-09-30
申请人： INTEL CORPORATION , RAMANUJAN, Raj, K. , AGARWAL, Rajat , HINTON, Glenn, J.
发明人： RAMANUJAN, Raj, K. , AGARWAL, Rajat , HINTON, Glenn, J.
IPC分类号： G06F12/00 , G06F13/14 , G11C7/10
CPC分类号： G06F12/0811 , G06F12/0246 , G06F12/0806 , G06F12/0808 , G06F12/0815 , G06F12/0888 , G06F12/0893 , G06F2212/205 , G06F2212/283 , G06F2212/6046 , G06F2212/621 , G06F2212/7201 , G11C7/1045 , G11C7/1072 , G11C13/0004 , G11C14/0045
摘要： A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as "far memory." Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as "near memory." In one embodiment, the "near memory" is configured to operate in a plurality of different modes of operation including (but not limited to) a first mode in which the near memory operates as a memory cache for the far memory and a second mode in which the near memory is allocated a first address range of a system address space with the far memory being allocated a second address range of the system address space, wherein the first range and second range represent the entire system address space.
摘要翻译：描述了用于集成包括计算机系统内的非易失性存储器层的存储器和存储层级的系统和方法。在一个实施例中，PCMS存储器件被用作层次结构中的一个层，有时被称为“远存储器”。更高性能的存储器件，例如放置在远存储器之前的DRAM，并用于掩盖远存储器的一些性能限制。这些更高性能的存储器件被称为“接近存储器”。在一个实施例中，“近存储器”被配置为以多种不同的操作模式操作，包括（但不限于）其中近端存储器作为远存储器的存储器高速缓存操作的第一模式，以及第二模式其中所述近存储器被分配有系统地址空间的第一地址范围，所述远存储器被分配了所述系统地址空间的第二地址范围，其中所述第一范围和第二范围表示整个系统地址空间。

63. 发明申请

WO2013048500A1 APPARATUS AND METHOD FOR IMPLEMENTING A MULTI-LEVEL MEMORY HIERARCHY OVER COMMON MEMORY CHANNELS 审中-公开
标题翻译：用于在通用存储器通道上实现多级存储器层级的装置和方法
公开(公告)号：WO2013048500A1
公开(公告)日：2013-04-04
申请号：PCT/US2011/054436
申请日：2011-09-30
申请人： INTEL CORPORATION , RAMANUJAN, Raj, K. , ZIAKAS, Dimitrios , ZIMMERMAN, David, J. , KUMAR, Mohan, J. , SWAMINATHAN, Muthukumar, P. , COURY, Bassam, N.
发明人： RAMANUJAN, Raj, K. , ZIAKAS, Dimitrios , ZIMMERMAN, David, J. , KUMAR, Mohan, J. , SWAMINATHAN, Muthukumar, P. , COURY, Bassam, N.
IPC分类号： G06F13/14 , G06F12/00
CPC分类号： G06F12/0811 , G06F12/0238 , G06F12/08 , G06F12/0802 , G06F12/0848 , G06F12/0866 , G06F12/0897 , G06F13/1684 , G06F2212/2024 , G06F2212/304
摘要： A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as "far memory." Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as "near memory."
摘要翻译：描述了用于集成包括计算机系统内的非易失性存储器层的存储器和存储层级的系统和方法。在一个实施例中，PCMS存储器件被用作层次结构中的一个层，有时被称为“远存储器”。更高性能的存储器件，例如放置在远存储器之前的DRAM，并用于掩盖远存储器的一些性能限制。这些更高性能的存储器件被称为“接近存储器”。

64. 发明申请

WO2013048497A1 APPARATUS AND METHOD FOR IMPLEMENTING A MULTI-LEVEL MEMORY HIERARCHY 审中-公开
标题翻译：实现多层次记忆层次分析的装置和方法
公开(公告)号：WO2013048497A1
公开(公告)日：2013-04-04
申请号：PCT/US2011/054430
申请日：2011-09-30
申请人： INTEL CORPORATION , RAMANUJAN, Raj, K. , AGARWAL, Rajat , CHENG, Kai , POLEPEDDI, Taarinya , RAAD, Camille, C. , ZIMMERMAN, David, J. , SWAMINATHAN, Muthukumar, P. , ZIAKAS, Dimitrios , KUMAR, Mohan, J.
发明人： RAMANUJAN, Raj, K. , AGARWAL, Rajat , CHENG, Kai , POLEPEDDI, Taarinya , RAAD, Camille, C. , ZIMMERMAN, David, J. , SWAMINATHAN, Muthukumar, P. , ZIAKAS, Dimitrios , KUMAR, Mohan, J.
IPC分类号： G06F12/00 , G11C7/10
CPC分类号： G06F12/0811 , G06F12/0895 , G06F12/0897 , G06F2212/2024 , G06F2212/205 , G11C11/40615 , G11C14/009 , Y02D10/13
摘要： A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as "far memory." Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as "near memory."
摘要翻译：描述了用于集成包括计算机系统内的非易失性存储器层的存储器和存储层级的系统和方法。在一个实施例中，PCMS存储器件被用作层次结构中的一个层，有时被称为“远存储器”。更高性能的存储器件，例如放置在远存储器之前的DRAM，并用于掩盖远存储器的一些性能限制。这些更高性能的存储器件被称为“接近存储器”。

65. 发明申请

WO2007108904A2 SYSTEM AND METHOD FOR EDITING ONLINE DOCUMENTS 审中-公开
标题翻译：用于编辑在线文档的系统和方法
公开(公告)号：WO2007108904A2
公开(公告)日：2007-09-27
申请号：PCT/US2007/005160
申请日：2007-02-27
申请人： SONOLINK COMMUNICATIONS SYSTEMS, LLC , MATHEW, Boban , JOHN, Thomas , EVANS, Dagny
发明人： MATHEW, Boban , JOHN, Thomas , EVANS, Dagny
IPC分类号： G06F15/00
CPC分类号： G06F17/3089 , G06F17/24
摘要： A system and method for editing documents available over a Web session. For example, one embodiment of the method comprises: establishing a Web session with a user computer; receiving a user request to edit a document from the user computer, the document having a particular document type and stored on a remote computer; automatically downloading a copy of the document and one or more modules to the user computer, the one or more modules to perform the operations of: invoking an application associated with the document type on the user computer, the application to provide an interface allowing the user to edit the document on the user computer; monitoring the state of the document copy, the state including an indication as to whether the document copy has been modified by the user to create a modified document copy; automatically uploading the modified document copy to the remote computer responsive from an indication that the document copy has been modified.
摘要翻译：用于编辑通过Web会话可用的文档的系统和方法。例如，该方法的一个实施例包括：与用户计算机建立Web会话; 接收用户从用户计算机编辑文档的请求，该文档具有特定文档类型并存储在远程计算机上; 自动将所述文档的副本和一个或多个模块下载到所述用户计算机，所述一个或多个模块执行以下操作：在所述用户计算机上调用与所述文档类型相关联的应用，所述应用提供允许所述用户在用户计算机上编辑文档; 监视文档副本的状态，该状态包括用户是否修改了文档副本以创建修改的文档副本的指示; 自动将修改的文档副本自动上传到远程计算机，从文档副本的修改指示。

66. 发明申请

WO2007044502A2 APPARATUS AND METHOD FOR PERFORMING MOTION CAPTURE USING A RANDOM PATTERN ON CAPTURE SERVICES 审中-公开
标题翻译：用于在捕捉服务上使用随机模式来执行运动捕捉的装置和方法
公开(公告)号：WO2007044502A2
公开(公告)日：2007-04-19
申请号：PCT/US2006/039093
申请日：2006-10-05
申请人： REARDEN, INC. , COTTER, Tim, S. , PERLMAN, Stephen, G. , SPECK, John , VAN DER LAAN, Roger , PEARCE, Ken, A. , LASALLE, Greg
发明人： COTTER, Tim, S. , PERLMAN, Stephen, G. , SPECK, John , VAN DER LAAN, Roger , PEARCE, Ken, A. , LASALLE, Greg
IPC分类号： H04N7/18 , H04N5/30 , H04N5/225
CPC分类号： G06T13/40 , G06K9/3216 , G06K2009/3225 , G06T7/20 , G06T7/246 , G06T7/292 , G06T2207/10016 , G06T2207/30196 , H04N5/2224 , H04N5/2256 , H04N5/2353 , H04N5/2354 , H04N5/247 , H04N13/239
摘要： A method is described comprising: applying a random pattern to specified regions of an object; tracking the movement of the random pattern during a motion capture session; and generating motion data representing the movement of the object using the tracked movement of the random pattern.
摘要翻译：描述了一种方法，包括：将随机模式应用于对象的指定区域; 在动作捕捉会话期间跟踪随机模式的移动; 并使用跟踪的随机模式移动来生成表示对象移动的运动数据。

67. 发明申请

WO2007005816A2 LOW-TEMPERATURE CATALYZED FORMATION OF SEGMENTED NANOWIRE OF DIELECTRIC MATERIAL 审中-公开
标题翻译：介电材料分段纳米线的低温催化生成
公开(公告)号：WO2007005816A2
公开(公告)日：2007-01-11
申请号：PCT/US2006/025957
申请日：2006-06-29
申请人： INTEL CORPORATION , LU, Donghui , CHEN, Zhan
发明人： LU, Donghui , CHEN, Zhan
IPC分类号： C30B25/00 , C30B11/12 , C30B29/38 , C30B29/60
CPC分类号： C30B25/005 , C30B11/12 , C30B25/105 , C30B29/38 , C30B29/605
摘要： The present invention discloses a method of forming a segmented nanowire including: providing a substrate; pre-cleaning the substrate; pre-treating the substrate; forming and placing a catalyst over the substrate; and forming the segmented nanowire over the catalyst with recurring pulses of plasma-enhanced chemical vapor deposition (PECVD) of a dielectric material.
摘要翻译：本发明公开了一种形成分段纳米线的方法，包括：提供衬底; 预清洁衬底; 预处理基材; 在基底上形成并放置催化剂; 和在介电材料的等离子体增强化学气相沉积（PECVD）的循环脉冲上形成分段纳米线。

68. 发明申请

WO2022271251A1 APPARATUS AND METHOD FOR COHERENT ERROR MITIGATION USING CLIFFORD GATE INJECTION 审中-公开
公开(公告)号：WO2022271251A1
公开(公告)日：2022-12-29
申请号：PCT/US2022/023131
申请日：2022-04-01
申请人： INTEL CORPORATION
发明人： PREMARATNE, Shavindra , SCHMITZ, Albert , MATSUURA, Anne , ZOU, Xiang
IPC分类号： G06N10/70 , G06N10/20 , G06F11/14 , G06N10/00 , H03K19/003
摘要： Apparatus and method for actively mitigating coherent errors by modifying an original quantum circuit, inserting Clifford gate operations at intermediate stages. Embodiments of the apparatus and method may perform CGI statically, at the compiling stage, and/or dynamically, at the control processing stage. The insertion of Clifford gates takes advantage of the symmetries in a quantum circuit and actively cancels coherent errors, maintaining the quantum processor in a state as close as possible to the original tune-up environment.

69. 发明申请

WO2022204418A1 APPARATUS AND METHOD FOR MANAGING UNSUPPORTED INSTRUCTION SET ARCHITECTURE (ISA) FEATURES IN A VIRTUALIZED ENVIRONMENT 审中-公开
公开(公告)号：WO2022204418A1
公开(公告)日：2022-09-29
申请号：PCT/US2022/021770
申请日：2022-03-24
申请人： INTEL CORPORATION
发明人： SONDAG, Tyler , SHEFFIELD, David , PEDIADITAKI, Sofia
IPC分类号： G06F9/455 , G06F9/30
摘要： Apparatus and method supporting deprecated instructions. One embodiment comprises: a plurality of cores, each core comprising a current microarchitecture to execute instructions and process data, the current microarchitecture including virtual execution environment support for a hypervisor running at a first privilege level and one or more virtual machines running at a second privilege level, the microarchitecture further including support for executing deprecated instructions associated with a prior microarchitecture. At least one core comprising: a decoder to specify one or more microoperations corresponding to each of the instructions; execution circuitry to execute the corresponding microoperations; wherein either a first type or a second type of virtual machine exit is supported. Responsive to the first type of virtual machine exit, the hypervisor performs a first emulation without the partial hardware support. Responsive to the second type of virtual machine exit, the hypervisor perform a second emulation using the partial hardware support.

70. 发明申请

WO2022066176A1 QUANTUM COMPUTING SYSTEMS, APPARATUS, AND METHODS 审中-公开
公开(公告)号：WO2022066176A1
公开(公告)日：2022-03-31
申请号：PCT/US2020/052944
申请日：2020-09-25
申请人： INTEL CORPORATION , PELLERANO, Stefano , HULL, Christopher , MLADENOV, Todor , PARK, JongSeok , KLOCHKOV, Ilya , SUBRAMANIAN, Sushil
发明人： PELLERANO, Stefano , HULL, Christopher , MLADENOV, Todor , PARK, JongSeok , KLOCHKOV, Ilya , SUBRAMANIAN, Sushil
IPC分类号： G06N10/00 , B82Y10/00
摘要： Apparatus and methods for interfacing an integrated qubit control chip and a solid state qubit; detecting a qubit state with a transition pulse histogram; high resolution and high speed rectangular pulse generation; large-scale spin qubit state readout; and activity-based clock control.

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