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41. 发明申请

WO2007038161A1 METHODS FOR MODULATING THE WORK FUNCTIONS OF FILM LAYERS 审中-公开
标题翻译：调制薄膜层功能的方法
公开(公告)号：WO2007038161A1
公开(公告)日：2007-04-05
申请号：PCT/US2006/036728
申请日：2006-09-20
申请人： SEMATECH, INC. , CHOI, Kisik , ALSHAREEF, Husam , MAJHI, Prashant
发明人： CHOI, Kisik , ALSHAREEF, Husam , MAJHI, Prashant
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842
摘要： Methods for fabricating two metal gate stacks with varying work functions for complementary metal oxide semiconductor (CMOS) devices are provided A first metal layer may be deposited onto a gate dielectric, followed by the deposition of a second metal layer, where the second metal layer modulated the work function of the first metal layer. The second metal layer and subsequently etch, exposing a portion of the first metal layer. A third metal layer may be deposited on the etched second metal layer and the exposed first metal layer, where the third metal layer may modulate the work function of the exposed first metal layer. Subsequent fabrication techniques were used to define the gate stack.
摘要翻译：提供了用于制造用于互补金属氧化物半导体（CMOS）器件的具有不同功函数的两个金属栅极叠层的方法。第一金属层可沉积在栅极电介质上，随后沉积第二金属层，其中第二金属层调制第一金属层的功函数。第二金属层并随后蚀刻，暴露第一金属层的一部分。可以在蚀刻的第二金属层和暴露的第一金属层上沉积第三金属层，其中第三金属层可以调节暴露的第一金属层的功函数。使用随后的制造技术来定义栅极堆叠。

42. 发明申请

WO2004092676A1 METHOD AND APPARATUS FOR DETERMINING THE THICKNESS OF A DIELECTRIC LAYER 审中-公开
标题翻译：用于确定介质层厚度的方法和装置
公开(公告)号：WO2004092676A1
公开(公告)日：2004-10-28
申请号：PCT/IB2004/050438
申请日：2004-04-14
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , MAJHI, Prashant
发明人： MAJHI, Prashant
IPC分类号： G01B7/06
CPC分类号： G01B7/06
摘要： The method for determining the thickness of a dielectric layer according to the invention comprises the step of providing an electrically conductive body (11) having a dielectric layer (13) which is separated from the electrically conductive body (11) by at least a further dielectric layer (3) and a surface (15) of which is exposed. Onto the exposed surface (15) an electric charge is deposited, thereby inducing an electric potential difference between the exposed surface (15) and the electrically conductive body (11). An electrical parameter relating to the electric potential difference is determined and a measurement is performed to obtain additional measurement data relating to the thickness of the dielectric layer (13) and/or to the thickness of the further dielectric layer (3). In this way the thickness of the dielectric layer (13) and/or of the further dielectric layer (3) is determined. The method of manufacturing an electric device (100) comprises this method for determining the thickness of a dielectric layer. The apparatus (10) for determining the thickness of a dielectric layer is arranged to execute this method.
摘要翻译：根据本发明的用于确定电介质层的厚度的方法包括提供具有电介质层（13）的导电体（11）的步骤，所述电介质层通过至少另外的电介质（13）与导电体（11）分离，层（3）和其表面（15）暴露。在暴露表面（15）上沉积电荷，从而在暴露表面（15）和导电体（11）之间产生电位差。确定与电位差有关的电参数，并进行测量以获得与介电层（13）的厚度和/或另外的电介质层（3）的厚度有关的附加测量数据。以这种方式确定电介质层（13）和/或另外的电介质层（3）的厚度。制造电气设备（100）的方法包括用于确定电介质层的厚度的方法。用于确定电介质层的厚度的装置（10）被布置成执行该方法。

43. 发明申请

WO2018236353A1 EMBEDDED NON-VOLATILE MEMORY BASED ON FERROELECTRIC FIELD EFFECT TRANSISTORS 审中-公开
公开(公告)号：WO2018236353A1
公开(公告)日：2018-12-27
申请号：PCT/US2017/038378
申请日：2017-06-20
申请人： INTEL CORPORATION
发明人： KARPOV, Elijah V. , KALAVADE, Pranav , MAJHI, Prashant , DOYLE, Brian S.
IPC分类号： H01L29/78 , H01L29/66 , H01L29/51 , H01L27/11585 , H01L27/11539
CPC分类号： H01L29/516 , H01L27/11597 , H01L29/40111
摘要： Embedded non-volatile memory structures based on ferroelectric field effect transistors (FeFETs) are described. In an example, an integrated circuit structure includes a vertical arrangement of a plurality of gate electrodes in an inter-layer dielectric (ILD) layer above a substrate. A trench is through the vertical arrangement of a plurality of gate electrodes in the ILD layer, the trench having sidewalls. A ferroelectric oxide material is continuous along the sidewalls of the trench. The ferroelectric oxide material is in contact with the vertical arrangement of the plurality of gate electrodes. A semiconductor channel material is adjacent to the ferroelectric oxide material along the sidewalls of the trench.

44. 发明申请

WO2018182646A1 APPARATUS WITH MULTI-WAFER BASED DEVICE COMPRISING EMBEDDED ACTIVE DEVICES AND METHOD FOR FORMING SUCH 审中-公开
公开(公告)号：WO2018182646A1
公开(公告)日：2018-10-04
申请号：PCT/US2017/025173
申请日：2017-03-30
申请人： INTEL CORPORATION
发明人： PANCHOLI, Anup , MAJHI, Prashant , FISCHER, Paul B. , MORROW, Patrick
IPC分类号： H01L21/768 , H01L21/762 , H01L23/00
摘要： An apparatus is provided which comprises: a substrate; a first active device adjacent to the substrate; a first set of one or more layers to interconnect the one or more active devices; a second set of one or more layers; a second active device coupled to the second set of one or more layers; and a layer adjacent to one of the layers of the first set and the second active device, wherein the layer is to bond the one of the layers of the first set and the second active device.

45. 发明申请

WO2018044256A1 RESISTIVE RANDOM ACCESS MEMORY DEVICES 审中-公开
标题翻译：随机访问存储器设备
公开(公告)号：WO2018044256A1
公开(公告)日：2018-03-08
申请号：PCT/US2016/049196
申请日：2016-08-29
申请人： INTEL CORPORATION
发明人： MAJHI, Prashant , PILLARISETTY, Ravi , KARPOV, Elijah V. , MUKHERJEE, Niloy , CLARKE, James S.
IPC分类号： H01L45/00
CPC分类号： H01L27/2436 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/145 , H01L45/146 , H01L45/16
摘要： Disclosed herein are resistive random access memory (RRAM) devices, and related memory cells and electronic devices. In some embodiments, an RRAM device may include a bottom electrode, an oxygen exchange layer (OEL), and an oxide layer. The bottom electrode may be disposed between the OEL and a substrate, and the OEL may be disposed between the oxide layer and the bottom electrode.
摘要翻译：这里公开的是电阻式随机存取存储器（RRAM）器件，以及相关的存储器单元和电子器件。在一些实施例中，RRAM器件可以包括底部电极，氧气交换层（OEL）和氧化物层。底部电极可以设置在OEL和衬底之间，并且OEL可以设置在氧化物层和底部电极之间。

46. 发明申请

WO2018022027A1 ARRAY INTERCONNECTS FOR RRAM DEVICES AND METHODS OF FABRICATION 审中-公开
标题翻译：用于RRAM器件的阵列互连和制造方法
公开(公告)号：WO2018022027A1
公开(公告)日：2018-02-01
申请号：PCT/US2016/044112
申请日：2016-07-26
申请人： INTEL CORPORATION
发明人： SHAH, Uday , KARPOV, Elijah V. , MAJHI, Prashant , PILLARISETTY, Ravi , MUKHERJEE, Niloy , CLARKE, James S. , INDUKURI, Tejaswi K. , ATANASOV, Sarah E.
IPC分类号： H01L45/00
CPC分类号： H01L27/2463 , H01L27/2436 , H01L45/08 , H01L45/1233 , H01L45/124 , H01L45/146 , H01L45/1675
摘要： In an embodiment, a resistive random access memory cell includes a plurality of conductive interconnects disposed in a first dielectric layer above a substrate. A plurality of RRAM devices is disposed in a second dielectric layer and each of the RRAM devices are coupled to a corresponding one of the plurality of conductive interconnects. A dielectric spacer surrounds each of the plurality of RRAM devices and extends from a bottom most surface of the second dielectric layer to an uppermost surface of the second dielectric layer. An interconnect is disposed in a trench of a third dielectric layer and coupled to the plurality of RRAM devices. The interconnect includes a diffusion barrier layer disposed at a bottom of and along sidewalls of the trench and a conductive fill layer disposed on the diffusion barrier layer. Uppermost surfaces of the conductive fill layer and the diffusion barrier layer are coplanar.
摘要翻译：在一个实施例中，电阻随机存取存储器单元包括设置在衬底上方的第一电介质层中的多个导电互连。多个RRAM器件设置在第二介电层中，并且每个RRAM器件耦合到多个导电互连中相应的一个。介电间隔物围绕多个RRAM器件中的每一个，并且从第二介电层的最底表面延伸到第二介电层的最上表面。互连设置在第三介电层的沟槽中并且耦合到多个RRAM器件。互连件包括设置在沟槽的底部并沿沟槽的侧壁的扩散阻挡层和设置在扩散阻挡层上的导电填充层。导电填充层和扩散阻挡层的最上面的表面是共面的。

47. 发明申请

WO2018009182A1 RESISTIVE RAM WITH ELECTROFORMING FUNCTIONALITY 审中-公开
标题翻译：具有电成形功能的电阻式RAM
公开(公告)号：WO2018009182A1
公开(公告)日：2018-01-11
申请号：PCT/US2016/041096
申请日：2016-07-06
申请人： INTEL CORPORATION
发明人： KARPOV, Elijah , BIELEFELD, Jeffery D. , KOTLYAR, Roza , MAJHI, Prashant , PILLARISETTY, Ravi
IPC分类号： H01L45/00 , G11C13/00
CPC分类号： G11C13/0007 , G11C13/003 , G11C2013/0083 , G11C2213/50 , G11C2213/52 , G11C2213/75 , H01L27/2463 , H01L45/085 , H01L45/1206 , H01L45/1233
摘要： A resistive RAM memory cell and array are described that include an electroforming functionally. One example includes a first resistive memory material, a first electrode on one side of the first resistive memory material, a second resistive memory material, a second electrode on one side of the second resistive memory material, a middle electrode between the first electrode and the second electrode, the middle electrode electrically coupled to the first resistive memory material on a side of the first resistive memory material opposite the first electrode and electrically coupled to the second resistive memory material and on a side of the second resistive memory material opposite the second electrode, and a power connector to apply a potential to the middle electrode, the potential being opposite a potential of the first electrode and the second electrode.
摘要翻译：描述了一种电阻式RAM存储器单元和阵列，其在功能上包括电铸。一个示例包括第一电阻式存储器材料，在第一电阻式存储器材料的一侧上的第一电极，第二电阻式存储器材料，在第二电阻式存储器材料的一侧上的第二电极，在第一电极和第二电阻式存储器材料之间的中间电极第二电极，中间电极在第一电阻存储器材料的与第一电极相对的一侧上电耦合到第一电阻存储器材料并且电耦合到第二电阻存储器材料并且在第二电阻存储器材料的与第二电极相对的一侧上以及用于向中间电极施加电位的电源连接器，该电位与第一电极和第二电极的电位相反。

48. 发明申请

WO2018009155A1 RRAM DEVICES HAVING A BOTTOM OXYGEN EXCHANGE LAYER AND THEIR METHODS OF FABRICATION 审中-公开
标题翻译：具有底部氧交换层的RRAM器件及其制造方法
公开(公告)号：WO2018009155A1
公开(公告)日：2018-01-11
申请号：PCT/US2016/040888
申请日：2016-07-02
申请人： INTEL CORPORATION
发明人： SHAH, Uday , PILLARISETTY, Ravi , KARPOV, Elijah V. , MUKHERJEE, Niloy , CLARKE, James S. , ATANASOV, Sarah , MAJHI, Prashant
IPC分类号： H01L45/00
摘要： Resistive random access memory (RRAM) devices having a bottom oxygen exchange layer and their methods of fabrication are described. In an example, an RRAM cell includes a conductive interconnect disposed in a first dielectric layer above a substrate. An RRAM device is coupled to the conductive interconnect and includes a bottom electrode layer formed above the conductive interconnect. An oxygen exchange metal layer is formed on the bottom electrode layer. A switching layer is formed on the oxygen exchange metal layer. A first dielectric hardmask layer is formed on the switching layer and includes an opening. A portion of a top electrode layer is formed in the opening, on the oxygen exchange metal layer. A top electrode fill metal layer is formed on the top electrode layer.
摘要翻译：描述了具有底部氧交换层的电阻随机存取存储器（RRAM）器件及其制造方法。在一个示例中，RRAM单元包括设置在衬底上方的第一电介质层中的导电互连。 RRAM器件耦合到导电互连并且包括形成在导电互连上方的底部电极层。氧气交换金属层形成在底部电极层上。在氧交换金属层上形成开关层。第一电介质硬掩模层形成在开关层上并且包括开口。顶部电极层的一部分形成在氧气交换金属层上的开口中。顶部电极填充金属层形成在顶部电极层上。

49. 发明申请

WO2018009154A1 RRAM DEVICES WITH EXTENDED SWITCHING LAYER AND METHODS OF FABRICATION 审中-公开
标题翻译：具有扩展开关层的RRAM器件和制造方法
公开(公告)号：WO2018009154A1
公开(公告)日：2018-01-11
申请号：PCT/US2016/040887
申请日：2016-07-02
申请人： INTEL CORPORATION
发明人： PILLARISETTY, Ravi , KARPOV, Elijah V. , SHAH, Uday , MUKHERJEE, Niloy , MAJHI, Prashant , INDUKURI, Tejaswi K. , CLARKE, James S.
IPC分类号： H01L45/00
摘要： Approaches for integrating a switching layer that is continuous across an array of RRAM (RRAM) cells and the resulting structures, are described. In an example, a RRAM (RRAM) cell includes an RRAM device coupled to a conductive interconnect disposed in a dielectric layer above the substrate. An RRAM device includes a bottom electrode coupled to an oxygen exchange layer and a top electrode through a switching layer. The switching layer physically extends over the dielectric layer and the bottom electrodes associated with all RRAM devices in a given array. A dielectric spacer film is disposed on the sidewalls of the memory device extending from a lowermost portion of the oxygen exchange layer to the uppermost portion of the top electrode.
摘要翻译：描述了用于集成在RRAM（RRAM）单元阵列上连续的交换层和所得结构的方法。在一个示例中，RRAM（RRAM）单元包括耦合到设置在衬底上方的电介质层中的导电互连的RRAM器件。 RRAM器件包括通过开关层耦合到氧气交换层和顶部电极的底部电极。开关层物理地延伸在介电层和与给定阵列中的所有RRAM器件相关联的底部电极之上。电介质隔离膜设置在存储器件的侧壁上，从氧交换层的最低部分延伸到顶电极的最高部分。

50. 发明申请

WO2017052583A1 THERMALLY INSULATED RESISTIVE RANDOM ACCESS MEMORY 审中-公开
标题翻译：热绝缘电阻随机存取存储器
公开(公告)号：WO2017052583A1
公开(公告)日：2017-03-30
申请号：PCT/US2015/052198
申请日：2015-09-25
申请人： INTEL CORPORATION
发明人： KARPOV, Elijah V. , SHAH, Uday , MAJHI, Prashant , MUKHERJEE, Niloy , PILLARISETTY, Ravi
IPC分类号： H01L27/115
CPC分类号： H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/08 , H01L45/085 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/16
摘要： An embodiment includes a resistive random access memory (RRAM) comprising: a top electrode portion and a bottom electrode portion; and an oxide layer between the top and bottom electrode portions; wherein (a) a conductive filament is within the oxide layer and is adjacent the top electrode portion, (b) the oxide layer includes oxide layer sidewalls, (c) a vertical axis intersects the oxide layer and the top and bottom electrode portions and is parallel to the oxide layer sidewalls, and (d) a void, which includes air, is adjacent the oxide layer sidewalls. Other embodiments are described herein.
摘要翻译：实施例包括电阻随机存取存储器（RRAM），其包括：顶部电极部分和底部电极部分; 以及在所述顶部和底部电极部分之间的氧化物层; 其中（a）导电丝在氧化物层的内部并与顶部电极部分相邻，（b）氧化物层包括氧化物层侧壁，（c）垂直轴与氧化物层和顶部和底部电极部分相交，并且是平行于氧化物层侧壁，和（d）包含空气的空隙与氧化物层侧壁相邻。本文描述了其它实施例。

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