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31. 发明申请

WO0219108A3 METHOD FOR PROVIDING BITWISE CONSTRAINTS FOR TEST GENERATION 审中-公开
标题翻译：提供用于测试生成的双向约束的方法
公开(公告)号：WO0219108A3
公开(公告)日：2002-07-25
申请号：PCT/IL0100803
申请日：2001-08-28
申请人： VERISITY LTD , LAGOON VITALY , BARRUCH GUY
发明人： LAGOON VITALY , BARRUCH GUY
IPC分类号： G06F17/50 , G01R31/28 , G01R31/3183 , G06F20060101 , G06F11/00 , G06F11/22 , G06F17/10
CPC分类号： G01R31/318371 , G06F11/263
摘要： A method for enabling bitwise or bit slice constraints to be provided as part of the test generation process, by providing a language structure which enables these constraints to be expressed in a test generation language such as e code for example. The language structure for such bitwise constraints is then handled in a more flexible manner, such that the test generation process does not attempt to rigidly "solve" the expression containing the constraint as a function. Therefore, the propagation of constraints in such a structure do not necessarily need to be propagated from left to right, but instead are generated in a multi-directional manner.
摘要翻译：通过提供使得能够以诸如e代码的测试生成语言来表达这些约束的语言结构，能够提供作为测试生成过程的一部分的按位或位片限制的方法。然后，以更灵活的方式处理这种按位约束的语言结构，使得测试生成过程不试图将包含该约束的表达式作为一个功能刚性地“解决”。因此，这种结构中约束的传播不一定需要从左向右传播，而是以多方向的方式产生。

32. 发明申请

WO02019108A2 METHOD FOR PROVIDING BITWISE CONSTRAINTS FOR TEST GENERATION 审中-公开
标题翻译：建立测试创建的位级约束的方法
公开(公告)号：WO02019108A2
公开(公告)日：2002-03-07
申请号：PCT/IL2001/000803
申请日：2001-08-28
IPC分类号： G06F17/50 , G01R31/28 , G01R31/3183 , G06F20060101 , G06F11/00 , G06F11/22 , G06F17/10
CPC分类号： G01R31/318371 , G06F11/263
摘要： A method for enabling bitwise or bit slice constraints to be provided as part of the test generation process, by providing a language structure which enables these constraints to be expressed in a test generation language such as e code for example. The language structure for such bitwise constraints is then handled in a more flexible manner, such that the test generation process does not attempt to rigidly "solve" the expression containing the constraint as a function. Therefore, the propagation of constraints in such a structure do not necessarily need to be propagated from left to right, but instead are generated in a multi-directional manner.
摘要翻译：本发明涉及一种通过构建以语言表达这些约束的语言结构来在测试创建过程的框架内建立比特级或比特波长约束的方法。测试创建，如电子代码。然后，以更灵活的方式处理这些比特级约束的语言结构，以便测试创建过程不会试图严格地将包含约束的表达式作为约束条件。功能。因此，诸如上述结构的结构中的应力传播不一定从左到右发生，约束是多方向地产生的。

33. 发明申请

WO01038981A1 TEST PATTERN COMPRESSION FOR AN INTEGRATED CIRCUIT TEST ENVIRONMENT 审中-公开
标题翻译：集成电路测试环境的测试模式压缩
公开(公告)号：WO01038981A1
公开(公告)日：2001-05-31
申请号：PCT/US2000/031377
申请日：2000-11-15
IPC分类号： G01R31/3183 , G01R31/3185 , G06F11/22 , G06F11/00
CPC分类号： G01R31/318335 , G01R31/318371 , G01R31/318547
摘要： A method for compressing test patterns to be applied to scan chains in a circuit under test. The method includes generating symbolic expressions that are associated with scan cells within the scan chains. The symbolic expressions are created by assigning variables to bits on external input channels supplied to the circuit under test (60). Using symbolic simulation, the variables are applied to a decompressor to obtain the symbolic expressions. A test cube is created using a deterministic pattern that assigns values to the scan cells to test faults within the integrated circuit (60). A set of equations is formulated by equating the assigned values in the test cube to the symbolic expressions associated with the corresponding scan cell (64). The equations are solved to obtain the compressed test pattern (66).
摘要翻译：一种用于压缩被测电路中扫描链应用的测试图案的方法。该方法包括生成与扫描链内的扫描单元相关联的符号表达式。通过将变量分配给提供给被测电路（60）的外部输入通道上的位来创建符号表达式。使用符号仿真，将变量应用于解压缩器以获取符号表达式。使用确定性模式创建测试立方体，该模式为扫描单元分配值以测试集成电路中的故障（60）。通过将测试多维数据集中的分配值与与相应扫描单元格（64）相关联的符号表达式进行等价来表示一组方程式。求解等式以获得压缩测试图案（66）。

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