专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明申请

WO2004047326A1 METHOD AND DEVICE FOR FINE SYNCHRONIZATION OF A DIGITAL TELECOMMUNICATION RECEIVER 审中-公开
标题翻译：用于数字电信接收机精细同步的方法和设备
公开(公告)号：WO2004047326A1
公开(公告)日：2004-06-03
申请号：PCT/EP2002/012813
申请日：2002-11-15
申请人： TELECOM ITALIA S.P.A. , STMICROELECTRONICS S.R.L. , ETTORRE, Donato , GRAZIANO, Maurizio , MELIS, Bruno , FINOTELLO, Andrea , RUSCITTO, Alfredo
发明人： ETTORRE, Donato , GRAZIANO, Maurizio , MELIS, Bruno , FINOTELLO, Andrea , RUSCITTO, Alfredo
IPC分类号： H04B1/707
CPC分类号： H04B1/7085 , H04B1/70757
摘要： A method for the synchronization of a digital telecommunication receiver comprises the steps of: - storing a plurality of consecutive samples E-l, E, M, L, L+1 of an incoming spread spectrum signal in a delay line 56; - determining by interpolation between consecutive samples of the incoming spread spectrum signal, by means of a first digitally controlled interpolator 26, an interpolated early sample (e) anticipating an optimal sampling time instant; - determining by interpolation between consecutive samples of the incoming spread spectrum signal, by means of a second digitally controlled interpolator 24, an interpolated middle sample (m) corresponding to the optimal sampling time instant; - determining by interpolation between consecutive samples of the incoming spread spectrum signal, by means of a third digitally controlled interpolator 28, an interpolated late sample (1) delayed with respect to the optimal sampling time instant; - calculating an error signal ξ as the difference between the energy of the symbols computed from the interpolated early sample (e) and the interpolated late (1) sample; - extracting the sign of the error signal ξ - accumulating the sign of the error signal ξ for the generation of control signals S E , S M , S L for controlling the interpolation phases of the digitally controlled interpolators used for determining the interpolated early (e), middle (m) and late (l) samples. The accumulated value has a positive saturation value of +4 and a negative saturation value of 4.
摘要翻译：一种用于数字电信接收机同步的方法包括以下步骤： - 在延迟线56中存储输入扩频信号的多个连续样本E-1，E，M，L，L + 1; - 通过第一数字控制内插器26来确定进入的扩频信号的连续采样之间的插值，预测最佳采样时刻的内插早期采样（e）; - 通过第二数字控制内插器24确定进入的扩频信号的连续采样之间的插值，对应于最佳采样时刻的内插中间采样（m）; - 通过第三数字控制内插器28确定进入的扩展频谱信号的连续样本之间的内插，相对于最佳采样时刻延迟的内插后采样（1）; 将误差信号xi计算为从插值的早期样本（e）和插值的深（1）样本计算的符号的能量之间的差; - 提取误差信号xi的符号 - 累积误差信号xi的符号以产生控制信号S> E <，S> M <，S> L <用于控制用于数字控制内插器的内插相位确定内插的早期（e），中（m）和晚（l）样本。累积值的正饱和值为+4，负饱和值为4。

22. 发明申请

WO2008064705A1 A DELAY ELEMENT AND A CORRESPONDING METHOD 审中-公开
标题翻译：延迟元素和相应的方法
公开(公告)号：WO2008064705A1
公开(公告)日：2008-06-05
申请号：PCT/EP2006/011498
申请日：2006-11-30
申请人： PIRELLI & C. S.P.A. , TELECOM ITALIA S.P.A. , GRASSANO, Giuseppe , BOFFA, Vincenzo , GATTI, Fabrizio , RISI, Luca , RUSCITTO, Alfredo , SEMENZATO, Paolo
发明人： GRASSANO, Giuseppe , BOFFA, Vincenzo , GATTI, Fabrizio , RISI, Luca , RUSCITTO, Alfredo , SEMENZATO, Paolo
IPC分类号： H01P5/18 , H01P9/00
CPC分类号： H01P5/184 , H01P9/00
摘要： A differential delay element (10) for use e.g. in selectively delaying RF signals in telecommunication systems includes a first microstrip circuit (12) and a second microstrip circuit (14) arranged side-by-side in a facing relationship. The first microstrip circuit (12) defines a first delayed travel path for a first signal from a first input port (IN1 ) to a first output port (OUT1 ) and the second microstrip circuit (14) defines a second delayed travel path for a second signal from a second input port (IN2) to a second output port (OUT2). A perturber (18) is arranged between the first (12) and second (14) microstrip circuits, displaceable (20) towards and away from the first (12) and second (14) microstrip circuits, so that when the distance of the perturber (18) to one (12 resp. 14) of the microstrip circuits increases, the distance of the perturber (18) to the other (14 resp. 12) of the microstrip circuits decreases and viceversa. The position of the perturber (18) between the first (12) and second (14) microstrip circuits defines the differential delay, namely the difference (Δτ=τ1-τ2) between the times (τ1, τ2) experienced by the two signals in travelling their travel paths through the delay device (10).
摘要翻译：一种差分延迟元件（10），用于例如在电信系统中选择性地延迟RF信号包括以面对关系并排布置的第一微带电路（12）和第二微带电路（14）。第一微带电路（12）限定用于从第一输入端口（IN1）到第一输出端口（OUT1）的第一信号的第一延迟行进路径，并且第二微带电路（14）限定第二延迟行进路径用于第二输入端口信号从第二输入端口（IN2）传输到第二输出端口（OUT2）。在第一（12）和第二（14）微带电路之间布置有一个扰流器（18），朝向和远离第一（12）和第二（14）微带电路可移位（20），使得当扰流器（18）到微带电路之一（12或14）增加，微带电路的静音（18）到另一个（14或12）的距离减小，反之亦然。第一（12）和第二（14）微带电路之间的谐振器（18）的位置定义差分延迟，即由两个信号经历的时间（t1，t2）之间的差值（Δt= t1-t2）在通过延迟装置（10）行进其行进路径时。

23. 发明申请

WO2009068051A1 TUNABLE RIDGE WAVEGUIDE DELAY LINE 审中-公开
公开(公告)号：WO2009068051A1
公开(公告)日：2009-06-04
申请号：PCT/EP2007/010318
申请日：2007-11-28
申请人： PIRELLI & C. S.P.A. , TELECOM ITALIA S.P.A. , BOFFA, Vincenzo , GRASSANO, Giuseppe , GATTI, Fabrizio , ACCATTINO, Luciano , BERTIN, Giorgio , RUSCITTO, Alfredo , SEMENZATO, Paolo
发明人： BOFFA, Vincenzo , GRASSANO, Giuseppe , GATTI, Fabrizio , ACCATTINO, Luciano , BERTIN, Giorgio , RUSCITTO, Alfredo , SEMENZATO, Paolo
IPC分类号： H01P1/18 , H01P9/00
CPC分类号： H01P9/00 , H01P1/182
摘要： A tunable delay line (100) for radiofrequency or microwave frequency applications consists of at least one ridge waveguide in which the ridge (103) is movable in the waveguide body (102) so as to vary the width of an air gap (105) defined between the longitudinal end surface of the ridge (103) and a confronting member (104) of the waveguide. The ridge (103) is moved by an actuator external to the waveguide body (102).
摘要翻译：用于射频或微波频率应用的可调延迟线（100）包括至少一个脊波导，其中脊（103）可在波导体（102）中移动，以便改变限定的气隙（105）的宽度在脊（103）的纵向端表面和波导的面对构件（104）之间。脊（103）由波导体（102）外部的致动器移动。

24. 发明申请

WO2008052580A1 MANAGEMENT OF SEAMLESS HANDOVER BETWEEN DIFFERENT COMMUNICATION SYSTEMS IN AN IP DUAL-MODE TERMINAL 审中-公开
标题翻译： IP双向终端不同通信系统之间的无缝切换管理
公开(公告)号：WO2008052580A1
公开(公告)日：2008-05-08
申请号：PCT/EP2006/010468
申请日：2006-10-31
申请人： TELECOM ITALIA S.P.A. , FANTINI, Roberto , CAZZATELLO, Gaetano, Francesco , RUSCITTO, Alfredo
发明人： FANTINI, Roberto , CAZZATELLO, Gaetano, Francesco , RUSCITTO, Alfredo
IPC分类号： H04L29/06 , H04Q7/32 , H04Q7/38
CPC分类号： H04L29/12028 , H04L61/103 , H04L69/16 , H04L69/161 , H04W8/26 , H04W36/0033 , H04W36/14 , H04W80/04 , H04W88/06
摘要： Disclosed herein is a dual-mode terminal (T1) designed to connect to an IP-based network (IPN) via a first communication system (UMTS) and a second communication system (WLAN), the dual-mode terminal (T1 ) comprising a first physical network interface module (N11) adapted to establish a packet-based communication with the IP-based network (IPN) via the first communication system (UMTS), the first physical network interface module (N11) being accessible via a first physical network interface (ph11 ) having a first physical network address (IP1_P1 ); a second physical network interface module (N11 ) adapted to establish a packet-based communication with the IP-based network via the second communication system (WLAN), the second physical network interface module (N 12) being accessible via a second physical network interface (ph12) having a second physical network address (IP1_P2); an IP-based protocol stack (TCP/IP) adapted to operate between a software application (A2) in the dual-mode terminal (T1) and the first and second physical network interface modules (N 11, N 12); and a system for performing a seamless handover between the first communication system (UMTS) and the second communication system (WLAN) during a connection to the IP-based network; wherein the system for performing a seamless handover comprises a virtual network physical network interface module (M 1 ) accessible via a virtual network interface (virt11) having a virtual network address (IP1 V1), the virtual network physical network interface module (M1) being configured to operate between the IP-based protocol stack (TCP/IP) and the first and second physical network interface modules (N11, N 12) to receive and transmit incoming and outgoing data packets through the first and the second physical network interfaces (ph11, ph12); the IP-based protocol stack (TCP/IP) being configured to generate data packets having a source physical network address equal to the virtual network address (IP1_V1) of the virtual network interface (virt11) in the dual-mode terminal (T1 ); and the virtual network physical network interface module (M 1) being configured to change the source physical network address of data packets from the IP-based protocol stack (IPS1 ) to the physical network address (IP1_P1, IP1_P2) of the physical network interface (ph11, ph12) of the physical network interface module (N11, N12) in the dual-mode terminal (T1 ) used for the connection to the IP-based network.
摘要翻译：本文公开了一种被设计为经由第一通信系统（UMTS）和第二通信系统（WLAN）连接到基于IP的网络（IPN）的双模终端（T1），所述双模终端（T1）包括第一物理网络接口模块（N11），其适于经由所述第一通信系统（UMTS）与所述基于IP的网络（IPN）建立基于分组的通信，所述第一物理网络接口模块（N11）可经由第一物理网络接口（ph11）具有第一物理网络地址（IP1_P1）; 适于经由所述第二通信系统（WLAN）与所述基于IP的网络建立基于分组的通信的第二物理网络接口模块（N11），所述第二物理网络接口模块（N12）可经由第二物理网络接口（ph12）具有第二物理网络地址（IP1_P2）; 适于在双模终端（T1）中的软件应用程序（A2）与第一和第二物理网络接口模块（N11，N12）之间操作的基于IP的协议栈（TCP / IP）; 以及在与所述基于IP的网络的连接期间在所述第一通信系统（UMTS）和所述第二通信系统（WLAN）之间执行无缝切换的系统; 其特征在于，所述用于执行无缝切换的系统包括经由具有虚拟网络地址（IP1 V1）的虚拟网络接口（virt11））可访问的虚拟网络物理网络接口模块（M 1），所述虚拟网络物理网络接口模块被配置为在基于IP的协议栈（TCP / IP）和第一和第二物理网络接口模块（N11，N12）之间操作，以通过第一和第二物理网络接口（ph11）接收和发送输入和输出数据分组，ph12）; 所述基于IP的协议栈（TCP / IP）被配置为生成具有等于所述双模终端（T1）中的虚拟网络接口（virt11）的虚拟网络地址（IP1_V1）的源物理网络地址的数据分组; 虚拟网络物理网络接口模块（M 1）被配置为将数据分组的源物理网络地址从基于IP的协议栈（IPS1）改变为物理网络接口的物理网络地址（IP1_P1，IP1_P2）用于连接到基于IP的网络的双模终端（T1）中的物理网络接口模块（N11，N12）的ph11，ph12，ph12）。

25. 发明申请

WO2003007195A3 SYSTEM AND METHOD FOR MAKING COMPLEX ELECTRONIC CIRCUITS 审中-公开
公开(公告)号：WO2003007195A3
公开(公告)日：2003-01-23
申请号：PCT/IT2002/000450
申请日：2002-07-09
申请人： TELECOM ITALIA S.P.A. , GARINO, Pierangelo , RICCIATO, Fabio , RUSCITTO, Alfredo , TUROLLA, Maura , VARRIALE, Antonio
发明人： GARINO, Pierangelo , RICCIATO, Fabio , RUSCITTO, Alfredo , TUROLLA, Maura , VARRIALE, Antonio
IPC分类号： G06F17/50
摘要： The present invention relates to a system (10) and method for making electronic circuits comprising elements or elementary circuit blocks which can be implemented either in the form of physical circuits, for instance FPGA, or in the form of firmware, for instance memorised on microprocessor. Thanks to the methodology used to describe the circuit blocks (26a, 26b) and their functional models (21), the system (10) and method allow to execute with a WS (11) and an emulator subsystem (30), in a single integrated environment, both the functional simulation of the model of complex electronic circuit and the emulation of the electronic circuit itself. Moreover, thanks to the characteristics of intrinsic congruence between the circuit blocks (26a, 26b) and their models (21), the emulation of the complex electronic circuit can be effected using alternatively circuit blocks implemented on the emulator subsystem either in the form of hardware (26a) or in the form of firmware (26b).

26. 发明申请

WO2009084051A1 MANAGEMENT OF A HYBRID COMMUNICATION NETWORK COMPRISING A CELLULAR NETWORK AND A LOCAL NETWORK 审中-公开
标题翻译：包含细胞网络和本地网络的混合通信网络的管理
公开(公告)号：WO2009084051A1
公开(公告)日：2009-07-09
申请号：PCT/IT2007/000928
申请日：2007-12-28
申请人： TELECOM ITALIA S.P.A. , FANTINI, Roberto , GALLO, Paolo , RUSCITTO, Alfredo
发明人： FANTINI, Roberto , GALLO, Paolo , RUSCITTO, Alfredo
IPC分类号： H04Q7/38 , H04Q7/32
CPC分类号： H04W48/18 , H04L5/006 , H04L67/32 , H04W28/0236 , H04W28/18 , H04W40/08 , H04W40/12 , H04W72/1226
摘要： Disclosed herein is a method of managing a hybrid network comprising a cellular network (3) and a local network (4) wherein a number of dual mode mobile terminals (7) are connectable to a base.station (10) of the cellular network (3) through a direct cellular link and are also connectable, one with respect to the other, through the local network (4) by means of a radio access technique. The method comprises the steps of computing a cost associated with a direct connection established along a path (A) extending from a selected mobile terminal to the base station (10) trough the cellular link only; computing a cost (C cg ) associated with at least one indirect connection established along a path (B) extending from said selected mobile terminal to said base station (10) trough the local network (4) and the cellular network (3) and selecting for data transmission the path that minimizes the cost.
摘要翻译：本文公开了一种管理包括蜂窝网络（3）和本地网络（4）的混合网络的方法，其中多个双模移动终端（7）可连接到蜂窝网络的基站（10）（10） 3）通过直接蜂窝链路，并且也可以通过无线电接入技术通过本地网络（4）彼此连接。该方法包括以下步骤：仅通过蜂窝链路来计算沿着从所选移动终端延伸到基站（10）的路径（A）建立的直接连接的成本; 计算与通过本地网络（4）和蜂窝网络（3）从所述选择的移动终端延伸到所述基站（10）的路径（B）建立的至少一个间接连接相关联的成本（Ccg），并且选择数据传输最小化成本的路径。

27. 发明申请

WO2009043378A1 METHOD AND SYSTEM FOR RADIATING A RADIOELECTRIC SIGNAL THROUGH A COMBINATION OF SECTOR ANTENNAS 审中-公开
标题翻译：通过组合天线辐射放射性信号的方法和系统
公开(公告)号：WO2009043378A1
公开(公告)日：2009-04-09
申请号：PCT/EP2007/060534
申请日：2007-10-04
申请人： TELECOM ITALIA S.p.A. , GIANOLA, Paolo , VALLAURI, Roberto , BOLLEA, Loris , RUSCITTO, Alfredo
发明人： GIANOLA, Paolo , VALLAURI, Roberto , BOLLEA, Loris , RUSCITTO, Alfredo
IPC分类号： H04B7/06
CPC分类号： H04B7/0671 , H04B7/0682
摘要： A method of radiating a radioelectric signal in an area of interest composed of at least two different area sectors, the method comprising: providing at least two sector antennas (130 1 ,130 2 ;530 1 , 530 2 ,530 3 ) arranged to cover the at least two different area sectors; feeding the at least two sector antennas with respective feed signals obtained from said signal; spacing apart the at least two sector antennas from each other of a distance ( d ) equal to or greater than one wavelength of a radioelectric signal to be irradiated; and acting on the feed signals fed to the at least two sector antennas in such a way that a relative phase of signals transmitted by the at least two sector antennas is caused to vary in time.
摘要翻译：一种在由至少两个不同区域扇区组成的感兴趣区域中辐射放射线电信号的方法，所述方法包括：提供至少两个扇形天线（1301,1302; 5301,5322,5303），被布置成覆盖所述至少两个不同的区域地区; 用从所述信号获得的各个馈送信号馈送所述至少两个扇区天线; 将所述至少两个扇形天线彼此间隔开等于或大于要照射的放射线电信号的一个波长的距离（d）; 并且以这样的方式作用于馈送到所述至少两个扇区天线的馈送信号，使得由所述至少两个扇区天线发射的信号的相对相位在时间上变化。

28. 发明申请

WO2003017084A2 MULTIPLIER CIRCUIT 审中-公开
标题翻译： MULTIPLIER电路
公开(公告)号：WO2003017084A2
公开(公告)日：2003-02-27
申请号：PCT/IT2002/000540
申请日：2002-08-14
申请人： TELECOM ITALIA LAB S.P.A. , ETTORRE, Donato , MELIS, Bruno , RUSCITTO, Alfredo
发明人： ETTORRE, Donato , MELIS, Bruno , RUSCITTO, Alfredo
IPC分类号： G06F7/52
CPC分类号： G06F7/523 , G06F2207/3852
摘要： An iterative multiplier circuit (10) comprises modules (15 to 18) that subdivide the respective input signals (Z n , J n ) into a first part (msb(Z n ), msb(J n )) that is the power of 2 immediately lower or equal to the input signal and a second part (Z n -msb(Z n ), J n - msb(J n )) corresponding to the difference between the input signal and the aforesaid first part. A shift module (19) generates a respective output signal through shift operations that implement the multiplication operation for numbers that are powers of 2. The circuit operates according to a general iterative scheme in which at each step three components of the output signal (X.Y) are computed, corresponding to the product of two numbers that are powers of 2 and to two products in which at least one of the factors is a power of 2. The number of steps in the iteration scheme is controllable, thus allowing to vary the accuracy with which the output value (X.Y) is calculated.
摘要翻译：迭代乘法器电路（10）包括将相应输入信号（Zn，Jn）细分为第二部分（msb（Zn），msb（Jn））的模块（15至18），其为2的功率立即下降或相等与输入信号和上述第一部分之间的差相对应的输入信号和第二部分（Zn-msb（Zn），Jn-msb（Jn））。移位模块（19）通过对作为功率为2的数字实施乘法运算的移位运算产生相应的输出信号。该电路根据通常的迭代方案运行，其中在每个步骤输出信号（XY）的三个分量被计算，对应于作为2的幂的两个数字的乘积和至少一个因子是2的幂的两个乘积。迭代方案中的步数可以被控制，从而允许改变精度计算输出值（XY）。

29. 发明申请

WO2003017085A2 POWER RAISING CIRCUIT 审中-公开
标题翻译：功率放大电路
公开(公告)号：WO2003017085A2
公开(公告)日：2003-02-27
申请号：PCT/IT2002/000539
申请日：2002-08-14
申请人： TELECOM ITALIA LAB S.P.A. , ETTORRE, Donato , MELIS, Bruno , RUSCITTO, Alfredo
发明人： ETTORRE, Donato , MELIS, Bruno , RUSCITTO, Alfredo
IPC分类号： G06F7/552
CPC分类号： G06F7/552 , G06F2207/3852 , G06F2207/5523
摘要： An iterative power raising circuit, such as a squarer (10) comprises a module (13, 14) able to subdivide the respective input signal (Z n ) into a first part (msb(Z n )) that is the power of 2 immediately lower than or equal to the input signal and a second part (Z n - msb(Z n )) corresponding to the difference between the respective input signal and the first part. A first component of the output signal is determined as the summation of squares of powers of 2 implemented by inserting zeros between the adjacent bits of the input binary signal (X). A shifter module (15) generates an additional component of the output signal through shift operations that implement multiplication operations for numbers that are powers of 2. The circuit operates according to a general iterative scheme and the number of steps in the iteration scheme is selectively controllable in order selectively to vary the precision with which the output value (Y) is calculated.
摘要翻译：诸如平方器（10）的迭代功率提升电路包括能够将相应的输入信号（Zn）细分成第二部分（msb（Zn））的模块（13,14），其是2的功率，其立即低于或等于输入信号的第二部分（Zn-msb（Zn））和与第一部分之间的差相对应的第二部分（Zn-msb（Zn））。输出信号的第一分量被确定为通过在输入二进制信号（X）的相邻位之间插入零而实现的功率2的平方的和。移位器模块（15）通过对作为功率为2的数字执行乘法运算的移位运算产生输出信号的附加分量。该电路根据一般迭代方案运行，并且迭代方案中的步数可以选择性地控制以便有选择地改变计算出输出值（Y）的精度。

30. 发明申请

WO2003007195A2 SYSTEM AND METHOD FOR MAKING COMPLEX ELECTRONIC CIRCUITS 审中-公开
标题翻译：制造复杂电子电路的系统和方法
公开(公告)号：WO2003007195A2
公开(公告)日：2003-01-23
申请号：PCT/IT2002/000450
申请日：2002-07-09
申请人： TELECOM ITALIA LAB S.P.A. , GARINO, Pierangelo , RICCIATO, Fabio , RUSCITTO, Alfredo , TUROLLA, Maura , VARRIALE, Antonio
发明人： GARINO, Pierangelo , RICCIATO, Fabio , RUSCITTO, Alfredo , TUROLLA, Maura , VARRIALE, Antonio
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5022
摘要： The present invention relates to a system (10) and method for making electronic circuits comprising elements or elementary circuit blocks which can be implemented either in the form of physical circuits, for instance FPGA, or in the form of firmware, for instance memorised on microprocessor. Thanks to the methodology used to describe the circuit blocks (26a, 26b) and their functional models (21), the system (10) and method allow to execute with a WS (11) and an emulator subsystem (30), in a single integrated environment, both the functional simulation of the model of complex electronic circuit and the emulation of the electronic circuit itself. Moreover, thanks to the characteristics of intrinsic congruence between the circuit blocks (26a, 26b) and their models (21), the emulation of the complex electronic circuit can be effected using alternatively circuit blocks implemented on the emulator subsystem either in the form of hardware (26a) or in the form of firmware (26b).
摘要翻译：本发明涉及一种用于制造包括元件或元件电路块的电子电路的系统（10）和方法，所述元件或基本电路块可以以物理电路（例如FPGA）的形式或以固件的形式实现，例如存储在微处理器。由于用于描述电路块（26a，26b）及其功能模型（21）的方法，所以系统（10）和方法允许以单一的方式（WS）（11）和仿真器子系统（30）执行综合环境，复杂电子电路模型的功能仿真和电子电路本身的仿真。此外，由于电路块（26a，26b）和它们的型号（21）之间的固有一致性的特征，复合电子电路的仿真可以使用在仿真器子系统上实现的电路块或硬件形式的硬件（26a）或固件（26b）的形式。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式