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21. 发明申请

WO2013173550A1 FUSING CONDITIONAL WRITE INSTRUCTIONS HAVING OPPOSITE CONDITIONS IN INSTRUCTION PROCESSING CIRCUITS, AND RELATED PROCESSOR SYSTEMS, METHODS, AND COMPUTER-READABLE MEDIA 审中-公开
标题翻译：在指令处理电路中具有对准条件的状态写入指令以及相关处理器系统，方法和计算机可读介质
公开(公告)号：WO2013173550A1
公开(公告)日：2013-11-21
申请号：PCT/US2013/041290
申请日：2013-05-16
申请人： QUALCOMM INCORPORATED
发明人： BROWN, Melinda J. , DIEFFENDERFER, James Norris , MCILVAINE, Michael Scott , STEMPEL, Brian Michael , SMITH, Rodney Wayne , SCHOTTMILLER, Jeffery M. , IRWIN, Andrew S. , MORROW, Michael William
IPC分类号： G06F9/30
CPC分类号： G06F9/3867 , G06F9/30043 , G06F9/30072 , G06F9/3017
摘要： Fusing conditional write instructions having opposite conditions in instruction processing circuits and related processor systems, methods, and computer-readable media are disclosed. In one embodiment, a first conditional write instruction writing a first value to a target register based on evaluating a first condition is detected by an instruction processing circuit. The circuit also detects a second conditional write instruction writing a second value to the target register based on evaluating a second condition that is a logical opposite of the first condition. Either the first condition or the second condition is selected as a fused instruction condition, and corresponding values are selected as if-true and if-false values. A fused instruction is generated for selectively writing the if-true value to the target register if the fused instruction condition evaluates to true, and selectively writing the if-false value to the target register if the fused instruction condition evaluates to false.
摘要翻译：公开了在指令处理电路和相关处理器系统，方法和计算机可读介质中具有相反条件的条件写指令。在一个实施例中，由指令处理电路检测基于评估第一条件将第一值写入目标寄存器的第一条件写入指令。该电路还基于评估与第一条件逻辑相反的第二条件来检测将第二值写入目标寄存器的第二条件写入指令。选择第一个条件或第二个条件作为融合指令条件，并将相应的值选为if-true和if-false值。如果融合指令条件评估为真，则生成融合指令，以便如果融合指令条件评估为真，则将if-true值有选择地写入目标寄存器，如果融合指令条件评估为false，则选择性地将if-false值写入目标寄存器。

22. 发明申请

WO2007085011A2 EFFICIENT MEMORY HIERARCHY MANAGEMENT 审中-公开
标题翻译：有效的记忆层级管理
公开(公告)号：WO2007085011A2
公开(公告)日：2007-07-26
申请号：PCT/US2007/060815
申请日：2007-01-22
申请人： QUALCOMM INCORPORATED , MORROW, Michael William , SARTORIUS, Thomas Andrew
发明人： MORROW, Michael William , SARTORIUS, Thomas Andrew
IPC分类号： G06F9/38
CPC分类号： G06F9/3802 , G06F12/0848
摘要： In a processor, there are situations where instructions and some parts of a program may reside in a data cache prior to execution of the program. Hardware and software techniques are provided for fetching an instruction in the data cache after having a miss in an instruction cache to improve the processor's performance. If an instruction is not present in the instruction cache, an instruction fetch address is sent as a data fetch address to the data cache. If there is valid data present in the data cache at the supplied instruction fetch address, the data actually is an instruction and the data cache entry is fetched and supplied as an instruction to the processor complex. An additional bit may be included in an instruction page table to indicate on a miss in the instruction cache that the data cache should be checked for the instruction.
摘要翻译：在处理器中，在执行程序之前，存在指令和程序的某些部分可能驻留在数据高速缓存中的情况。提供硬件和软件技术，用于在指令高速缓存中未命中以提高处理器性能之后在数据高速缓存中获取指令。如果指令缓存中没有指令，则指令提取地址作为数据提取地址发送到数据缓存。如果在提供的取指地址的数据高速缓存中存在有效数据，则数据实际上是一条指令，并且数据高速缓存条目被提取并作为指令提供给处理器组合系统。指令页表中可能包含一个额外的位，以指示指令缓存中的未命中数据缓存应该检查该指令。

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