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21. 发明申请

WO1997040394A1 APPARATUS FOR PERFORMING LOGIC AND LEAKAGE CURRENT TESTS ON A DIGITAL LOGIC CIRCUIT 审中-公开
标题翻译：用于在数字逻辑电路上执行逻辑和漏电流测试的装置
公开(公告)号：WO1997040394A1
公开(公告)日：1997-10-30
申请号：PCT/US1997000974
申请日：1997-01-17
申请人： CREDENCE SYSTEMS CORPORATION
发明人： CREDENCE SYSTEMS CORPORATION , MILLER, Charles, A.
IPC分类号： G01R31/28
CPC分类号： G01R31/3004 , G01R31/31924
摘要： An apparatus for performing logic and leakage current tests on a logic circuit device under test (DUT) includes a local module (14) for each terminal of the DUT. For performing logic tests, each local module has a driver for supplying a logic signal input to the DUT terminal, a comparator (82) for detecting the DUT output at the terminal, and a clamping circuit (22) for limiting the voltage swing at the DUT terminal during the logic test. For performing a leakage current test, each local module (14) includes a source for supplying a parametric signal to the DUT terminal. The voltage the parametric signal produces at the DUT terminal, as detected by the comparator (82) indicates the terminal's leakage current. The parametric signal source (24) and the clamping circuit (22) are connected to the DUT terminal through Schottky diodes (52, 54). During a logic test the parametric signal source (24) is isolated from the DUT terminal by reverse biasing the Schottky diodes linking the parametric signal source (24) to the DUT terminal.
摘要翻译：用于在待测逻辑电路器件（DUT）上执行逻辑和漏电流测试的装置包括用于DUT的每个端子的本地模块（14）。对于执行逻辑测试，每个本地模块具有用于向DUT端子提供逻辑信号输入的驱动器，用于检测端子处的DUT输出的比较器（82）和用于限制在该端子处的电压摆幅的钳位电路（22） DUT端子在逻辑测试期间。为了执行泄漏电流测试，每个本地模块（14）包括用于向DUT终端提供参数信号的源。由比较器（82）检测的参量信号在DUT端产生的电压表示端子的漏电流。参数信号源（24）和钳位电路（22）通过肖特基二极管（52,54）连接到DUT端子。在逻辑测试期间，通过将连接参数信号源（24）的肖特基二极管与DUT端子反向偏置，参数信号源（24）与DUT端子隔离。

22. 发明申请

WO1997025796A1 CLOCK SIGNAL DESKEWING SYSTEM 审中-公开
标题翻译：时钟信号降温系统
公开(公告)号：WO1997025796A1
公开(公告)日：1997-07-17
申请号：PCT/US1996019622
申请日：1996-12-10
申请人： CREDENCE SYSTEMS CORPORATION
发明人： CREDENCE SYSTEMS CORPORATION , BEDELL, Daniel, J. , MILLER, Charles, A.
IPC分类号： H04L07/00
CPC分类号： H04L7/0337 , H04L7/0008 , H04L7/0037 , H04L7/0041
摘要： A system (10) for distributing synchronized clock signals to spatially distributed circuits (15) includes a pair of transmission lines (16, 18) between first (14) and second (24) sites. Deskewing circuits tap the signal transmission lines between the first and second sites. A first delay circuit (DELAY) in each deskewing circuit detects the outgoing clock signal on the first line and produceds a local clock signal (CLKL) that lags the outgoing clock signal by an adjustable delay. A similar second delay circuit in each deskewing circuit delays the local clock signal by a similar delay to produce a local reference signal. A phase lock controller (30) in each deskewing circuit adjusts the delay of the delay circuits so that the local reference signal is phase locked to the returning clock signal on the second line. When reference signals in all deskewing circuits are phase locked to the returning clock signal, their local clock signals have similar phases.
摘要翻译：用于将同步时钟信号分配给空间分布电路（15）的系统（10）包括在第一（14）和第二（24）站点之间的一对传输线（16,18）。倒塌电路分接第一和第二站点之间的信号传输线。每个去歪斜电路中的第一延迟电路（DELAY）检测第一行上的输出时钟信号，并产生一个以可调延迟滞后于输出时钟信号的本地时钟信号（CLKL）。每个去歪斜电路中的类似的第二延迟电路使本地时钟信号延迟相似的延迟以产生局部参考信号。每个去歪斜电路中的锁相控制器（30）调节延迟电路的延迟，使得本地参考信号与第二行上的返回时钟信号锁相。当所有的偏移电路中的参考信号被锁相到返回的时钟信号时，它们的本地时钟信号具有相似的相位。

23. 发明申请

WO1997025664A1 SIGNAL DESKEWING SYSTEM FOR SYNCHRONOUS LOGIC CIRCUIT 审中-公开
标题翻译：用于同步逻辑电路的信号烧录系统
公开(公告)号：WO1997025664A1
公开(公告)日：1997-07-17
申请号：PCT/US1996019446
申请日：1996-12-05
申请人： CREDENCE SYSTEMS CORPORATION
发明人： CREDENCE SYSTEMS CORPORATION , MILLER, Charles, A.
IPC分类号： G06F01/12
CPC分类号： G01R31/31922 , G01R31/3191 , G06F1/10
摘要： A global clock signal (CLKG) is distributed to each module (16(1)-16(N)) of a distributed synchronous logic circuit via two separate transmission lines (18A, 18B) which are of similar length but have dissimilar velocities of signal propagation. A phase difference between corresponding pulses of the global clock signal arriving at each module is proportional to the length of the transmission lines and to the inherent clock signal delay in either transmission line. A deskewing circuit (18(1)-18(N)) at each module delays the global clock signal after it arrives at the module to produce a local clock signal (CLK(1)-CLK(N)). The deskewing circuit detects the phase difference between global clock signal pulses arriving at the module to determine the inherent delay of the first transmission line and then adjusts the local clock delay so that the sum of the inherent delay and local clock delay equals a standard delay.
摘要翻译：全局时钟信号（CLKG）通过两个分开的传输线（18A，18B）被分配到分布式同步逻辑电路的每个模块（16（1）-16（N）），两条分离的传输线（18A，18B）具有相似的长度但具有不同的信号速度传播。到达每个模块的全局时钟信号的相应脉冲之间的相位差与传输线的长度和传输线中固有的时钟信号延迟成比例。每个模块的歪斜电路（18（1）-18（N））在其到达模块之后延迟全局时钟信号以产生本地时钟信号（CLK（1）-CLK（N））。去歪斜电路检测到达模块的全局时钟信号脉冲之间的相位差，以确定第一传输线的固有延迟，然后调整本地时钟延迟，使得固有延迟和本地时钟延迟之和等于标准延迟。

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