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21. 发明申请

WO2003030263A1 SINGLE STEP CHEMICAL MECHANICAL POLISH PROCESS TO IMPROVE THE SURFACE ROUGHNESS IN MRAM TECHNOLOGY 审中-公开
标题翻译：单步化学机械抛光工艺改善MRAM技术中的表面粗糙度
公开(公告)号：WO2003030263A1
公开(公告)日：2003-04-10
申请号：PCT/US2002/003044
申请日：2002-01-24
申请人： INFINEON TECHNOLOGIES NORTH AMERICA CORP.
发明人： SENG, Low, Kia
IPC分类号： H01L27/22
CPC分类号： H01L43/12 , B82Y10/00 , H01L21/3212 , H01L27/222
摘要： A method of lithographically forming a semiconductor device that reduces the effects of edge topography when misalignment occurs. The method comprises forming a dielectric layer (20) having a top surface, etching a trench (22) in the dielectric layer and depositing a liner (26) on the top surface of the dielectric layer and within the trench. A metal layer (24) is then deposited on the liner and polishes until the metal layer is coplanar with the liner on the top surface of the dielectric layer, leaving a portion of the liner exposed. A stack layer (32) is deposited atop the exposed liner and on the polished metal layer and patterned. The exposed liner and non-patterned portion of the stack layer are removed simultaneously. A magnetic RAM (MRAM) can be processed in which undesirable magnetic properties caused by mis-alignment of the magnetic stack are minimized because of the improved edge topography.
摘要翻译：一种光刻形成半导体器件的方法，当发生不对准时减少边缘形貌的影响。该方法包括形成具有顶表面的电介质层（20），蚀刻电介质层中的沟槽（22），并在介质层的顶表面和沟槽内沉积衬垫（26）。然后将金属层（24）沉积在衬垫上并抛光，直到金属层与电介质层顶表面上的衬垫共面，留下衬套的一部分。堆叠层（32）沉积在暴露的衬垫顶部和抛光的金属层上并被图案化。堆叠层的暴露的衬垫和非图案化部分被同时移除。可以处理磁性RAM（MRAM），其中由于改进的边缘形貌，使磁性堆叠的错误对准引起的不期望的磁性能最小化。

22. 发明申请

WO2003003568A2 ACTIVE AUTO ZERO CIRCUIT FOR PROGRAMMABLE TIME CONTINUOUS OPEN LOOP AMPLIFIERS 审中-公开
标题翻译：可编程时间连续开环放大器的主动自动零电路
公开(公告)号：WO2003003568A2
公开(公告)日：2003-01-09
申请号：PCT/US2002/016738
申请日：2002-05-28
申请人： INFINEON TECHNOLOGIES NORTH AMERICA CORP.
发明人： BLON, Thomas , CYRUSIAN, Sasan
IPC分类号： H03F3/45
CPC分类号： H03F3/45197 , H03F3/45659 , H03F3/45753 , H03F2203/45616
摘要： An active offset cancellation circuit for an open loop differential amplifier having programmable gain is disclosed. The amplifier is operated on a two-phase clock where the normal operation occurs on the first phase and offset detection and cancellation occurs on the second phase. On the first phase, the programmable gain of the amplifier is set according to the application of the amplifier. On the second phase, the programmable gain of the amplifier is set to the maximum value and the offset cancellation circuit measures the offset created by the amplifier when both differential inputs are connected to a common source. The circuit then adjusts a bias current and stores this adjustment to cancel offset during the operational phase of the amplifier. During the operational phase, the first phase of the clock, the programmable gain is again returned to a value according to the application and the stored adjustment is used to bias the current in one of the two input stages of the amplifier, canceling any offset imparted by the amplifier circuitry. One each clock cycle, any additional offset is similarly detected and canceled. Further, by varying the gain as described, residual offset is reduced.
摘要翻译：公开了一种具有可编程增益的开环差分放大器的有源偏移消除电路。放大器工作在两相时钟，第一相出现正常工作，第二相发生偏移检测和取消。在第一阶段，根据放大器的应用设置放大器的可编程增益。在第二阶段，将放大器的可编程增益设置为最大值，并且当两个差分输入连接到公共源时，偏移消除电路测量由放大器产生的偏移。该电路然后调整偏置电流并存储该调整以在放大器的操作阶段消除偏移。在运行阶段，在时钟的第一阶段，根据应用，可编程增益再次返回到一个值，并且所存储的调整用于偏置放大器的两个输入级之一的电流，消除所赋予的任何偏移由放大器电路。一个每个时钟周期，任何额外的偏移量也被类似地检测和取消。此外，通过改变如所述的增益，剩余偏移减小。

23. 发明申请

WO2003003458A3 POWER PADS FOR APPLICATION OF HIGH CURRENT PER BOND PAD IN SILICON TECHNOLOGY 审中-公开
公开(公告)号：WO2003003458A3
公开(公告)日：2003-01-09
申请号：PCT/US2002/019095
申请日：2002-06-17
申请人： INFINEON TECHNOLOGIES AG
发明人： FRIESE, Gerald
IPC分类号： H01L23/58
摘要： A structure for a bond pad used on a semiconductor device, in accordance with the present invention, includes a metal layer, an interconnect formed through a dielectric layer connecting to the metal layer and a bond pad having a first portion disposed over the metal layer and the interconnect, and a second portion disposed over the dielectric layer. The first portion includes a bond area for providing an attachment point for a connection, and the second portion includes a probe area for providing contact with a probe.

24. 发明申请

WO2003003366A1 TOTAL ERROR MULTIPLIER FOR OPTIMIZING READ/WRITE CHANNEL 审中-公开
标题翻译：用于优化读/写通道的总错误乘法器
公开(公告)号：WO2003003366A1
公开(公告)日：2003-01-09
申请号：PCT/US2002/019089
申请日：2002-06-17
申请人： INFINEON TECHNOLOGIES NORTH AMERICA CORP.
发明人： BLISS, William, G. , RAE, James, W.
IPC分类号： G11B20/10
CPC分类号： G11B20/1816 , G11B20/10009 , G11B20/22
摘要： A method and apparatus to optimize a bit error rate for a partial response, maximum likelihood ("PRML") read/write channel is disclosed. A channel margining circuit (300) that is configured to carry out an embodiment for a method of optimizing the bit error rates of a read/write channel is described. The margining circuit derives an interference signal to stress a read/write channel for optimizing the bit error rate. The signal is derived from bit errors inherent with the read/write channel. The circuit reduces the time to optimize the channel by providing an amplified interference signal that increases a bit error rate during optimization.
摘要翻译：公开了一种用于优化部分响应，最大似然（“PRML”）读/写通道的误码率的方法和装置。描述了被配置为执行用于优化读/写通道的误码率的方法的实施例的通道裕度电路（300）。边缘电路导出干扰信号，以压缩读/写通道，以优化误码率。该信号来自读/写通道固有的位错误。该电路通过提供在优化期间增加误码率的放大干扰信号来减少对信道优化的时间。

25. 发明申请

WO2003001593A2 ALIGNED STI PROCESS USING NITRIDE HARD MASK 审中-公开
标题翻译：使用硝酸硬掩模的对准STI工艺
公开(公告)号：WO2003001593A2
公开(公告)日：2003-01-03
申请号：PCT/US2002/019892
申请日：2002-06-21
申请人： INFINEON TECHNOLOGIES NORTH AMERICA CORP.
发明人： POHL, John , CHAUDHARY, Nirmal , KLEE, Veit , MONO, Tobias , SCHROEDER, Paul
IPC分类号： H01L21/8242
CPC分类号： H01L27/10861 , H01L21/76224
摘要： A nitride hard mask (230) is used to isolate active areas of a DRAM cell. The shallow trench isolation (STI) method includes forming memory cells comprising deep trenches (216) on a semiconductor wafer (200). The memory cell deep trenches (216) are separated from active areas (212) by a region of substrate (212). A nitride hard mask (230) is formed over the semiconductor wafer (200). The wafer (200) is patterned with the nitride hard mask (230), and the wafer (200) is etched to remove the region of substrate (212) between the deep trenches and active areas to provide shallow trench isolation. An etch chemistry selective to the nitride hard mask (230) is used.
摘要翻译：氮化物硬掩模（230）用于隔离DRAM单元的有效区域。浅沟槽隔离（STI）方法包括在半导体晶片（200）上形成包括深沟槽（216）的存储单元。存储单元深沟槽（216）通过衬底（212）的区域与有源区域（212）分离。氮化物硬掩模（230）形成在半导体晶片（200）上。用氮化物硬掩模（230）对晶片（200）进行构图，并且蚀刻晶片（200）以去除深沟槽和有源区域之间的衬底（212）的区域，以提供浅沟槽隔离。使用对氮化物硬掩模（230）选择性的蚀刻化学品。

26. 发明申请

WO2002097999A1 HIGH-SPEED SAMPLE-AND-HOLD CIRCUIT WITH GAIN 审中-公开
标题翻译：高速采样和保持电路与增益
公开(公告)号：WO2002097999A1
公开(公告)日：2002-12-05
申请号：PCT/US2002/016763
申请日：2002-05-24
申请人： INFINEON TECHNOLOGIES NORTH AMERICA CORP.
发明人： BACH, Elmar , CYRUSIAN, Sasan
IPC分类号： H03M1/12
CPC分类号： G11C27/026 , G11C27/02 , H03M1/1245
摘要： A sample-and-hold system that includes a first source follower having an input and an output and a second source follower that includes an input connected in series with the output of the first source follower and that furthermore comprises of a sample-and-hold switch connected to an output of the second source follower.
摘要翻译：一种采样和保持系统，其包括具有输入和输出的第一源极跟随器和包括与第一源极跟随器的输出串联连接的输入的第二源极跟随器，并且还包括采样和保持开关连接到第二源极跟随器的输出端。

27. 发明申请

WO2002097998A3 ULTRA HIGH SPEED CLOCKED ANALOG LATCH 审中-公开
公开(公告)号：WO2002097998A3
公开(公告)日：2002-12-05
申请号：PCT/US2002/016092
申请日：2002-05-22
申请人： INFINEON TECHNOLOGIES AG
发明人： CYRUSIAN, Sasan
IPC分类号： H03K5/22
摘要： An ultra high-speed clocked analog latch is revealed for use at clock speeds from 100MHz to several GHz. The analog latch is used as a latching comparator for comparing a time-varying analog signal with an analog reference voltage. The latch uses CMOS manufacturing technology and a minimal amount of space for a two-stage amplifying and signal-generating device. The latch is useful in analog to digital converters (ADCs) in which high speed and high relability are required, but only a small amount of space is available. The device is so small and economical that several may be used in series to avoid any meta-stability problems in high-speed read/write operations.

28. 发明申请

WO2002097981A1 METHOD AND APPARATUS FOR AN EFFICIENT LOW VOLTAGE SWITCHABLE GM CELL 审中-公开
标题翻译：一种高效低电压切换GM电池的方法和装置
公开(公告)号：WO2002097981A1
公开(公告)日：2002-12-05
申请号：PCT/US2002/016762
申请日：2002-05-24
申请人： INFINEON TECHNOLOGIES NORTH AMERICA CORP.
发明人： CYRUSIAN, Sasan
IPC分类号： H03G3/00
CPC分类号： H03G1/0088 , H03F3/45188 , H03F3/45659 , H03F2203/45392 , H03F2203/45396 , H03F2203/45651 , H03G1/0029
摘要： A switching GM cell allowing a wide transconductance range with a limited voltage range. The GM cell includes a plurality of GM setting devices, the operation of which is controlled by a GM setting code. The GM setting code is inputted into a switching circuit which turns on and off at least one of said GM setting devices. Thus, coarse adjustments of the overall transconductance of the cell may be adjusted by hanging the GM setting code and fine adjustments may be made by utilizing the conventional method of adjusting a tuning voltage.
摘要翻译：开关型GM电池允许在有限电压范围内的宽跨导范围。 GM小区包括多个GM设置设备，其运行由GM设置代码控制。 GM设定码被输入切换电路，其切换至少一个所述GM设定装置。因此，可以通过悬挂GM设定代码来调整单元的整个跨导的粗调，并且可以通过利用调整调谐电压的常规方法进行微调。

29. 发明申请

WO2002097976A1 ULTRA HIGH SPEED CLOCKED LIMITING PREAMPLIFIER 审中-公开
标题翻译：超高速限时前置放大器
公开(公告)号：WO2002097976A1
公开(公告)日：2002-12-05
申请号：PCT/US2002/016759
申请日：2002-05-24
申请人： INFINEON TECHNOLOGIES NORTH AMERICA CORP.
发明人： CYRUSIAN, Sasan
IPC分类号： H03F3/45
CPC分类号： H03F3/4565 , H03F3/45192 , H03F3/45762
摘要： An ultra high-speed clocked limiting preamplifier is revealed, useful especially at speeds exceeding 1 GHz. The preamplifier is useful in comparing an analog input signal to a reference voltage, and then pre-amplifying the signal for further processing. The preamplifier is designed for accepting a time-varying input voltage, processing the signal through one or more stages of preamplification, and then converting the signal to a digital output. The preamplifier is useful in analog to digital converters (ADCs) and clock data recovery circuits.
摘要翻译：显示超高速时钟限制前置放大器，特别是在超过1 GHz的速度时尤其有用。前置放大器可用于将模拟输入信号与参考电压进行比较，然后对信号进行预放大以便进一步处理。前置放大器设计用于接受时变输入电压，通过一个或多个预放大级处理信号，然后将信号转换为数字输出。前置放大器在模数转换器（ADC）和时钟数据恢复电路中非常有用。

30. 发明申请

WO2002097974A3 ACTIVE AUTO ZERO CIRCUIT FOR TIME CONTINUOUS OPEN LOOP AMPLIFIERS 审中-公开
公开(公告)号：WO2002097974A3
公开(公告)日：2002-12-05
申请号：PCT/US2002/016631
申请日：2002-05-24
申请人： INFINEON TECHNOLOGIES NORTH AMERICA CORP.
发明人： BLON, Thomas , CYRUSIAN, Sasan
IPC分类号： H03F3/45
摘要： An active offset cancellation circuit for an open loop differential amplifier is disclosed. The amplifier is operated on a two-phase clock where the normal operation occurs on the first phase (PHI 1) and offset detection and cancellation occurs on the second phase. On the second phase, the offset cancellation circuit measures the offset created by the amplifier when both differential inputs (202, 204) are connected to a common source (VCMIN). The circuit then adjusts a bias current and stores this adjustment to cancel offset during the operational phase of the amplifier. During the operational phase, the first phase of the clock, the stored adjustment is used to bias the current in one of the two input stages of the amplifier (202, 204), canceling any offset imparted by the amplifier circuitry. One each clock cycle, any additional offset is similarly detected and canceled.

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