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11. 发明申请

WO0211377A9 CURRENT MODE TRANSMISSION 审中-公开
标题翻译：电流模式传输
公开(公告)号：WO0211377A9
公开(公告)日：2003-07-10
申请号：PCT/US0123646
申请日：2001-07-27
申请人： LYNK LABS INC , ANDERSEN JAMES NORMAN
发明人： ANDERSEN JAMES NORMAN
IPC分类号： H04L25/02 , H04L25/03
CPC分类号： H04L25/0282 , H04L25/0278 , H04L25/0294 , H04L25/03878
摘要： This invention relates to data communication equipment (DCE), more specifically, high speed transmission of electronic data between data terminal equipment (DTE). The invention sets forth a method and a device for transmitting a voltage signal waveform as a series of current pluses onto, for instance, a communication line. The method requires converting an input voltage signal waveform to a current signal waveform and transmitting the resulting current pulses onto a communication line wherein a predetermined bias voltage is maintained.
摘要翻译：本发明涉及数据通信设备（DCE），更具体地说，涉及数据终端设备（DTE）之间的电子数据的高速传输。本发明提出了一种用于将电压信号波形作为一系列电流信号发送到例如通信线路的方法和装置。该方法需要将输入电压信号波形转换为电流信号波形，并将得到的电流脉冲发送到保持预定偏置电压的通信线路上。

12. 发明申请

WO02058240A1 SELF-TERMINATING CURRENT MIRROR TRANSCEIVER LOGIC 审中-公开
标题翻译：自动终止电流收发器逻辑
公开(公告)号：WO02058240A1
公开(公告)日：2002-07-25
申请号：PCT/US2002/001613
申请日：2002-01-22
IPC分类号： H03K19/0175 , H04L25/02 , H03K17/16 , H03K19/003
CPC分类号： H04L25/0278 , H04L25/0282 , H04L25/0294
摘要： A self-terminating FET digital logic receiver (14) for impedance-matched interconnection to a transmission line (20) having a uniform characteristic impedance. First and second non-zero current level digital logic signals are received from the transmission line at an input terminal (22). A first current mirror FET (RM1) connected to the input terminal is configured to provide nonlinear current/voltage characteristics between the first and second current levels which approximate the characteristic impedance of the transmission line. The current of the digital logic signals is therefore absorbed by the first FET to minimize signal reflections on the transmission line. A second FET (RM2) is connected to the first FET to provide a mirror current having current levels proportional to the current levels of the digital logic signals. A load (RM3, RM4) is connected to the second FET produces voltage level signals representative of the digital logic signals.
摘要翻译：一种用于与具有均匀特性阻抗的传输线（20）进行阻抗匹配互连的自终端FET数字逻辑接收器（14）。在输入端（22）从传输线接收第一和第二非零电流电平数字逻辑信号。连接到输入端子的第一电流镜面FET（RM1）被配置为在接近传输线的特性阻抗的第一和第二电流水平之间提供非线性电流/电压特性。因此，数字逻辑信号的电流被第一FET吸收，以最小化传输线上的信号反射。第二FET（RM2）连接到第一FET以提供具有与数字逻辑信号的电流电平成比例的电流电平的镜电流。连接到第二FET的负载（RM3，RM4）产生代表数字逻辑信号的电压电平信号。

13. 发明申请

WO02011377A2 DATA TRANSMISSION APPARATUS AND METHOD 审中-公开
标题翻译：数据传输装置和方法
公开(公告)号：WO02011377A2
公开(公告)日：2002-02-07
申请号：PCT/US2001/023646
申请日：2001-07-27
IPC分类号： H04L25/02 , H04L25/03 , H04L25/00
CPC分类号： H04L25/0282 , H04L25/0278 , H04L25/0294 , H04L25/03878
摘要： This invention relates to data communication equipment (DCE), more specifically, high speed transmission of electronic data between data terminal equipment (DTE). The invention sets forth a method and a device for transmitting a voltage signal waveform as a series of current pluses onto, for instance, a communication line. The method requires converting an input voltage signal waveform to a current signal waveform and transmitting the resulting current pulses onto a communication line wherein a predetermined bias voltage is maintained.
摘要翻译：本发明涉及数据通信设备（DCE），更具体地说，涉及数据终端设备（DTE）之间的电子数据的高速传输。本发明提出了一种用于将电压信号波形作为一系列电流信号发送到例如通信线路的方法和装置。该方法需要将输入电压信号波形转换为电流信号波形，并将得到的电流脉冲发送到保持预定偏置电压的通信线路上。

14. 发明申请

WO0044140A2 METHOD AND DEVICE FOR DATA TRANSMISSION 审中-公开
标题翻译：方法和设备进行数据传输
公开(公告)号：WO0044140A2
公开(公告)日：2000-07-27
申请号：PCT/CH0000015
申请日：2000-01-11
申请人： METAPHYSICS S A , VOCKENHUBER PETER , WAGNIERES PHILIPPE
发明人： VOCKENHUBER PETER , WAGNIERES PHILIPPE
IPC分类号： H04L25/02 , H04L25/08
CPC分类号： H04L25/0266 , H04L25/0282 , H04L25/085
摘要： The device is provided with at least one information line (15, 15') for the transmission of information in the form of analog signals which are derived by a switch point or a sensor (8-11) coupled to the information line (15, 15') and fitted with an address detector (18) for reading address signals via a transformer (I4-I7) that converts the analog signals into a proportional current, wherein the transformer (I4-I7) is connectable to the information line (15, 15') by means of a switch (S1-S4) that is activatable by the corresponding address detector (S1-S4). A reference voltage source (13, 13') for the voltage of the information line (15, 15') is also provided and at least one derivation element (C1-C4) for deriving the overvoltages induced by external interferences from the information line (15, 15').
摘要翻译：在用于模拟信号，这些信号被转换成电流形式传输信息的方法，该电流强度正比于信号，对应于模拟信号在经由至少一个信息导体（15当前变量电流的形式的信息，15“是）传送时，电流被测量，并且（在一个比例信号到模拟信号P3）转换。的信息导体（15,15“）的电压维持在一个参考值，和通过诱导从信息导体（15，15的外部干扰的过电压”分别衍生）。具有“用于在由至少一个与所述信息导体（15，15提供的模拟信号的形式传输信息的耦合（通过），用于读出具有地址检测器的地址的信号。这些优选的装置的至少一个的信息导体（15，15）” 18）切换并提供给传感器（8-11）（通过电流互感器I4-I7）导出，其将模拟信号转换成上（成比例的电流，其中所述电流互感器（I4-I7）由相应的地址检测器18的装置）激活开关（S1-S4）与数据线（15，15“）是可连接的。另外，“用于信息导体（15，15的电压）被提供，并用于从外部噪声引起的过电压导出从信息管理器的至少一个转向元件（C1-C4）的参考电压源（13，13）”（15 '15）存在，

15. 发明申请

WO1993018462A1 HIGH SPEED BUS SYSTEM 审中-公开
标题翻译：高速总线系统
公开(公告)号：WO1993018462A1
公开(公告)日：1993-09-16
申请号：PCT/US1993001816
申请日：1993-03-03
申请人： RAMBUS, INC.
发明人： RAMBUS, INC. , HOROWITZ, Mark, Alan , LEE, Winston, K., M.
IPC分类号： G06F13/40
CPC分类号： H04L25/0298 , G06F13/4072 , H03K3/356043 , H04L25/0282 , Y02D10/14 , Y02D10/151
摘要： In the high speed bus system of the present invention, the bus configuration is one in which all master devices are clustered at one end of an unterminated end of the bus. The slaves are located along the remaining length of the bus and the opposite end of the transmission line of the bus is terminated. By eliminating the termination resistor at the end of the bus where the master devices are located the required drive current needed to produce a given output swing is reduced. The bus drivers and receivers are CMOS integrated circuits. The bus of the present invention is operable utilizing small swing signals which enable sufficient implementation of current mode drivers for low impedance bus signals. In particular, the bus input receiver of the present invention comprises a two stage buffered sampler/amplifier which receives a small swing signal from the bus and samples and amplifies the low swing signal to a full swing signal within a single clock cycle using CMOS circuits.
摘要翻译：在本发明的高速总线系统中，总线配置是其中所有主设备在总线的未端接端的一端集群的配置。从站沿着总线的剩余长度定位，并且总线的传输线的相对端终止。通过消除主设备所在总线末端的终端电阻，减少了产生给定输出摆幅所需的驱动电流。总线驱动器和接收器是CMOS集成电路。本发明的总线可利用小的摆动信号进行操作，这使得能够充分实现用于低阻抗总线信号的电流模式驱动器。特别地，本发明的总线输入接收机包括两级缓冲取样器/放大器，其从总线接收小的摆动信号，并使用CMOS电路在单个时钟周期内对低回波信号采样并放大到全摆幅信号。

16. 发明申请

WO2011073184A2 ACTIVE EYE OPENER FOR CURRENT-SOURCE DRIVEN, HIGH-SPEED SERIAL LINKS 审中-公开
标题翻译：用于电流源驱动的主动眼睛开启器，高速串行链接
公开(公告)号：WO2011073184A2
公开(公告)日：2011-06-23
申请号：PCT/EP2010069615
申请日：2010-12-14
申请人： ST ERICSSON SA , RAZZELL CHARLES , LIM HONG SAIR , OKUR BATUHAN , TJIA JEROME , WEE TUE FATT DAVID
发明人： RAZZELL CHARLES , LIM HONG SAIR , OKUR BATUHAN , TJIA JEROME , WEE TUE FATT DAVID
IPC分类号： H04B3/06 , H04L25/02
CPC分类号： H04B3/06 , H04L25/0282
摘要： A current boost circuit acts as an "eye opener" for a digital bus line. A controlled current injects a fraction of the normal signaling current magnitude from a source driver onto the bus line, after a transition between the two logical states on the bus line is detected. The duration of the additional current injection is a fraction of the unit interval. In one embodiment, a linear system uses the summation of a proportional boost current and a delayed and negated proportional boost current. In another embodiment, a positive or negative edge detection circuit triggers a monostable pulse generator that controls the injection of short bursts of additional current into the bus lines. In some embodiments the boost current is suppressed when the bus line is driven from a driver other than the source driver.
摘要翻译：电流升压电路充当数字总线的“开眼”。在检测到总线上的两个逻辑状态之间的转换之后，受控电流将来自源极驱动器的正常信号电流幅度的一部分注入到总线上。额外电流注入的持续时间是单位间隔的一小部分。在一个实施例中，线性系统使用比例升压电流和延迟和否定比例升压电流的总和。在另一个实施例中，正或负边缘检测电路触发单稳脉冲发生器，其控制向总线线路注入附加电流的短脉冲串。在一些实施例中，当总线从除源极驱动器之外的驱动器驱动时，升压电流被抑制。

17. 发明申请

WO2006133152A3 POWER LINE COMMUNICATION SYSTEM 审中-公开
标题翻译：电力线通信系统
公开(公告)号：WO2006133152A3
公开(公告)日：2007-06-21
申请号：PCT/US2006021861
申请日：2006-06-06
申请人： LUTRON ELECTRONICS CO , STEINER JAMES P , DOBBINS AARON , BLAIR EDWARD J
发明人： STEINER JAMES P , DOBBINS AARON , BLAIR EDWARD J
IPC分类号： H04B3/54
CPC分类号： H04L1/0054 , H04B3/54 , H04B2203/5412 , H04B2203/5416 , H04B2203/5458 , H04L1/0072 , H04L1/1812 , H04L25/0266 , H04L25/0282 , Y10T307/406
摘要： A system for independent control of electric motors and electric lights includes a plurality of two-wire wallstations coupled in series via power wires between an alternating-current (AC) source and a light/motor control unit. The light/motor control units is preferably located in the same enclosure as an electric motor5 and an electric light and has two outputs for independent control of the motor and the light. The light/motor unit and the wallstations each include a controller and a communication circuit that is coupled tot he power wiring via a communication transformer and communication with each other using a loop current carrier technique. The light/motor control unit and the wallstation utilize pseudo random orthogonal codes and a median filter in the communication process.
摘要翻译：用于独立控制电动机和电灯的系统包括通过交流（AC）源和光/电动机控制单元之间的电力线串联耦合的多个双线壁站。光/电动机控制单元优选地位于与电动机5和电灯相同的外壳中，并且具有用于马达和灯的独立控制的两个输出。光/电动机单元和壁台各自包括控制器和通信电路，其通过通信变压器耦合到电力布线并且使用环路电流载波技术彼此通信。光/电机控制单元和墙壁站在通信过程中利用伪随机正交码和中值滤波器。

18. 发明申请

WO2006081082A3 COMBINATION OF HIGH-SIDE AND LOW-SIDE CURRENT SENSING IN SYSTEM FOR PROVIDING POWER OVER COMMUNICATION LINK 审中-公开
标题翻译：用于提供通信链路的系统中的高边和低端电流感测的组合
公开(公告)号：WO2006081082A3
公开(公告)日：2007-03-08
申请号：PCT/US2006001283
申请日：2006-01-13
申请人： LINEAR TECHN INC , DWELLEY DAVID MCLEAN , HEATH JEFFREY LYNN
发明人： DWELLEY DAVID MCLEAN , HEATH JEFFREY LYNN
IPC分类号： H04L12/10 , G01R31/02 , H04L5/20 , H04L12/56 , H04L25/02
CPC分类号： H04L25/028 , H04L12/10 , H04L25/0282
摘要： A system for supplying power to a load (LOAD) over a communication link (between 14 and 16) has high-side current sensing circuitry for measuring a high-side current value, low-side current sensing circuitry for measuring a low-side current value, and control circuitry (18) responsive to both the high-side current value and the low-side current value to detect a fault condition, detect information from the load, and/or transmit information to the load by creating a prescribed unbalance between the high-side current and the low-side current.
摘要翻译：通过通信链路（14和16之间）向负载（LOAD）供电的系统具有用于测量高端电流值的高端电流检测电路，用于测量低端电流的低侧电流检测电路值和控制电路（18），其响应高端电流值和低侧电流值，以检测故障状况，从负载检测信息，和/或通过在负载之间产生规定的不平衡来向负载发送信息高边电流和低边电流。

19. 发明申请

WO2005055540A3 CURRENT TRANSFER LOGIC 审中-公开
标题翻译：电流传输逻辑
公开(公告)号：WO2005055540A3
公开(公告)日：2005-11-24
申请号：PCT/US2004037145
申请日：2004-11-08
申请人： PRADHAN PRAVAS , JU JIANHONG
发明人： PRADHAN PRAVAS , JU JIANHONG
IPC分类号： H04L25/02
CPC分类号： H04L25/0272 , H04L25/0278 , H04L25/0282 , H04L25/0294
摘要： A current mode transfer logic system suitable for driving transmission lines is disclosed. In one embodiment a twisted pair transmission line is terminated in its characteristic line impedance. A signal is formed of two unequal currents, preferably of different polarities as well as magnitudes, that are driven down the two lines. The unequal currents are selectively switched between the two lines creating a logic signal of a differential current drive of unequal current magnitudes. The unequal currents are received and shunted from the distal end of each line via diode connected MOS transistors. The MOS transistors are biased to present a low impedance, but an impedance higher than the terminating resistor. The currents are amplified and converted to useable CMOS voltage levels. In another embodiment the twisted pair is replaced by two parallel transmission lines which are terminated in one resistor, equal to the sum of the characteristic impedances of each line. The terminating resistor is connected between the distal signal carrying conductors of each transmission line. The shields or return paths for each line are tied together at the distal and at the proximate (drive) ends of the line.
摘要翻译：公开了适用于驱动传输线的电流模式传输逻辑系统。在一个实施例中，双绞线传输线在其特征线阻抗中终止。信号由两条不相等的电流形成，优选地具有不同的极性以及在两条线路上被驱动的幅度。在两条线之间选择性地切换不相等的电流，从而产生不等电流幅值的差动电流驱动的逻辑信号。通过二极管连接的MOS晶体管，从每条线的远端接收不相等的电流并分流。 MOS晶体管被偏置以呈现低阻抗，但阻抗高于终端电阻器。电流被放大并转换成可用的CMOS电压电平。在另一个实施例中，双绞线被两个平行的传输线代替，这两条并行传输线终止于一个电阻器中，等于每条线路的特征阻抗之和。终端电阻连接在每条传输线的远端信号承载导体之间。每条线的屏蔽或返回路径在线的远端和近端（驱动）端连接在一起。

20. 发明申请

WO2005043850A8 FLEXIBLE VERSATILE LOW-COST WIRELINE TRANSMIT DRIVER 审中-公开
标题翻译：灵活的低成本线路发射驱动器
公开(公告)号：WO2005043850A8
公开(公告)日：2005-07-28
申请号：PCT/US2004036155
申请日：2004-10-29
申请人： ANALOG DEVICES INC , MAULIK PRABIR C , HENDRIKS PAUL M , MEHR LURI
发明人： MAULIK PRABIR C , HENDRIKS PAUL M , MEHR LURI
IPC分类号： H04B3/00 , H04L25/00 , H04L25/02
CPC分类号： H04L25/028 , H04L25/0282 , H04L25/029
摘要： A versatile, programmable, low-cost transmit line driver is provided. The line driver includes a digital-to-analog converter that receives a digital input and provides an analog output. The line driver is reconfigurable between a voltage mode of operation and a current mode of operation.
摘要翻译：提供了多功能，可编程，低成本的传输线驱动器。线路驱动器包括数模转换器，其接收数字输入并提供模拟输出。线路驱动器可以在电压工作模式和当前工作模式之间进行重新配置。

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