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1. 发明申请

WO2011159583A4 COMPOSITION OF MEMORY CELL WITH RESISTANCE-SWITCHING LAYERS 审中-公开
标题翻译：具有电阻切换层的存储器单元的组成
公开(公告)号：WO2011159583A4
公开(公告)日：2012-08-02
申请号：PCT/US2011040105
申请日：2011-06-10
申请人： SANDISK 3D LLC , KREUPL FRANZ , BANDYOPADHYAY ABHIJIT , CHEN YUNG-TIN , FU CHU-CHEN , JAYASEKARA WIPUL PEMSIRI , KAI JAMES , MAKALA RAGHUVEER S , RABKIN PETER , SAMACHISA GEORGE , ZHANG JINGYAN
发明人： KREUPL FRANZ , BANDYOPADHYAY ABHIJIT , CHEN YUNG-TIN , FU CHU-CHEN , JAYASEKARA WIPUL PEMSIRI , KAI JAMES , MAKALA RAGHUVEER S , RABKIN PETER , SAMACHISA GEORGE , ZHANG JINGYAN
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： H01L27/2409 , G11C11/16 , G11C11/1659 , G11C13/0007 , G11C2213/31 , G11C2213/71 , G11C2213/72 , H01L27/2481 , H01L45/08 , H01L45/122 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146
摘要： A memory device in a 3-D read and write memory includes memory cells. Each memory cell includes a resistance-switching memory element (RSME) in series with a steering element. The RSME has first and second resistance-switching layers on either side of a conductive intermediate layer, and first and second electrodes at either end of the RSME. The first and second resistance-switching layers can both have a bipolar or unipolar switching characteristic. In a set or reset operation of the memory cell, an ionic current flows in the resistance-switching layers, contributing to a switching mechanism. An electron flow, which does not contribute to the switching mechanism, is reduced due to scattering by the conductive intermediate layer, to avoid damage to the steering element. Particular materials and combinations of materials for the different layers of the RSME are provided.
摘要翻译：三维读写存储器中的存储器件包括存储器单元。每个存储单元包括与转向元件串联的电阻切换存储元件（RSME）。 RSME在导电中间层的任一侧具有第一和第二电阻转换层，并且在RSME的任一端具有第一和第二电极。第一和第二电阻切换层都可以具有双极性或单极性切换特性。在存储器单元的置位或复位操作中，离子电流在电阻切换层中流动，从而有助于切换机制。由于导电中间层的散射，对开关机构没有贡献的电子流被减少，以避免损坏导向元件。提供了用于RSME的不同层的特定材料和材料的组合。

2. 发明申请

WO2011159583A3 COMPOSITION OF MEMORY CELL WITH RESISTANCE-SWITCHING LAYERS 审中-公开
标题翻译：具有电阻切换层的记忆体组成
公开(公告)号：WO2011159583A3
公开(公告)日：2012-06-14
申请号：PCT/US2011040105
申请日：2011-06-10
申请人： SANDISK 3D LLC , KREUPL FRANZ , BANDYOPADHYAY ABHIJIT , CHEN YUNG-TIN , FU CHU-CHEN , JAYASEKARA WIPUL PEMSIRI , KAI JAMES , MAKALA RAGHUVEER S , RABKIN PETER , SAMACHISA GEORGE , ZHANG JINGYAN
发明人： KREUPL FRANZ , BANDYOPADHYAY ABHIJIT , CHEN YUNG-TIN , FU CHU-CHEN , JAYASEKARA WIPUL PEMSIRI , KAI JAMES , MAKALA RAGHUVEER S , RABKIN PETER , SAMACHISA GEORGE , ZHANG JINGYAN
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： H01L27/2409 , G11C11/16 , G11C11/1659 , G11C13/0007 , G11C2213/31 , G11C2213/71 , G11C2213/72 , H01L27/2481 , H01L45/08 , H01L45/122 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146
摘要： A memory device in a 3-D read and write memory includes memory cells. Each memory cell includes a resistance-switching memory element (RSME) in series with a steering element. The RSME has first and second resistance-switching layers on either side of a conductive intermediate layer, and first and second electrodes at either end of the RSME. The first and second resistance-switching layers can both have a bipolar or unipolar switching characteristic. In a set or reset operation of the memory cell, an ionic current flows in the resistance-switching layers, contributing to a switching mechanism. An electron flow, which does not contribute to the switching mechanism, is reduced due to scattering by the conductive intermediate layer, to avoid damage to the steering element. Particular materials and combinations of materials for the different layers of the RSME are provided.
摘要翻译： 3-D读写存储器中的存储器件包括存储器单元。每个存储单元包括与转向元件串联的电阻切换存储元件（RSME）。 RSME在导电中间层的任一侧上具有第一和第二电阻切换层，在RSME的任一端具有第一和第二电极。第一和第二电阻切换层都可以具有双极或单极开关特性。在存储单元的置位或复位操作中，离子电流在电阻切换层中流动，有助于切换机构。由于导电中间层的散射，对切换机构无贡献的电子流减少，以避免损坏转向元件。提供了用于RSME不同层的材料和材料的组合。

3. 发明申请

WO2011159581A3 MEMORY CELL WITH RESISTANCE-SWITCHING LAYERS 审中-公开
标题翻译：具有电阻切换层的存储单元
公开(公告)号：WO2011159581A3
公开(公告)日：2012-04-19
申请号：PCT/US2011040103
申请日：2011-06-10
申请人： SANDISK 3D LLC , KREUPL FRANZ , COSTA XIYING , KAI JAMES , MAKALA RAGHUVEER S
发明人： KREUPL FRANZ , COSTA XIYING , KAI JAMES , MAKALA RAGHUVEER S
IPC分类号： H01L45/00 , H01L27/24
CPC分类号： H01L27/2409 , G11C11/16 , G11C11/1659 , G11C13/0007 , G11C2213/31 , G11C2213/71 , G11C2213/72 , H01L27/2481 , H01L45/08 , H01L45/122 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146
摘要： A memory device in a 3-D read and write memory includes memory cells. Each memory cell includes a resistance-switching memory element (RSME) in series with a steering element. The RSME has first and second resistance-switching layers on either side of a conductive intermediate layer, and first and second electrodes at either end of the RSME. The first and second resistance-switching layers can both have a bipolar or unipolar switching characteristic. In a set or reset operation of the memory cell, an electric field is applied across the first and second electrodes. An ionic current flows in the resistance-switching layers, contributing to a switching mechanism. An electron flow, which does not contribute to the switching mechanism, is reduced due to scattering by the conductive intermediate layer, to avoid damage to the steering element. Particular materials and combinations of materials for the different layers of the RSME are provided.
摘要翻译： 3-D读写存储器中的存储器件包括存储器单元。每个存储单元包括与转向元件串联的电阻切换存储元件（RSME）。 RSME在导电中间层的任一侧上具有第一和第二电阻切换层，在RSME的任一端具有第一和第二电极。第一和第二电阻切换层都可以具有双极或单极开关特性。在存储单元的置位或复位操作中，跨越第一和第二电极施加电场。离子电流在电阻切换层中流动，有助于切换机构。由于导电中间层的散射，对切换机构无贡献的电子流减少，以避免损坏转向元件。提供了用于RSME不同层的材料和材料的组合。

4. 发明申请

WO2012003301A3 ULTRAHIGH DENSITY VERTICAL NAND MEMORY DEVICE AND METHOD OF MAKING THEREOF 审中-公开
标题翻译：超高密度垂直NAND存储器件及其制造方法
公开(公告)号：WO2012003301A3
公开(公告)日：2012-04-19
申请号：PCT/US2011042566
申请日：2011-06-30
申请人： SANDISK TECHNOLOGIES INC , ALSMEIER JOHANN , PURAYATH VINOD , CHIEN HENRY , MATAMIS GEORGE , LEE YAO-SHENG , KAI JAMES , ZHANG YUAN , SAMACHISA GEORGE
发明人： ALSMEIER JOHANN , PURAYATH VINOD , CHIEN HENRY , MATAMIS GEORGE , LEE YAO-SHENG , KAI JAMES , ZHANG YUAN , SAMACHISA GEORGE
IPC分类号： H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/66833 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L27/11582 , H01L29/66825 , H01L29/78642 , H01L29/7889 , H01L29/7926
摘要： Monolithic, three dimensional NAND strings and manufacturing methods are disclosed. The channel (1) of the strings can be vertical or V-shaped. The core the channel can be filled with an insulator. The control gates ( 3 ) are recessed with respect to intermediate dielectric layers. The charge storage regions ( 9 ) and the blocking dielectric (7) are formed in the recesses. Shielding wings (12) can be formed next to the control gates.
摘要翻译：公开了单片三维NAND串和制造方法。弦的通道（1）可以是垂直的或V形的。通道的芯可以填充绝缘体。控制栅极（3）相对于中间介电层凹陷。电荷存储区（9）和阻挡电介质（7）形成在凹部中。屏蔽翼（12）可以在控制门旁边形成。

5. 发明申请

WO2008122012A3 INTEGRATED NON-VOLATILE MEMORY AND PERIPHERAL CIRCUITRY FABRICATION 审中-公开
标题翻译：集成的非易失性存储器和外围电路制造
公开(公告)号：WO2008122012A3
公开(公告)日：2008-11-20
申请号：PCT/US2008059035
申请日：2008-04-01
申请人： SANDISK CORP , KAI JAMES , PHAM TUAN , HIGASHITANI MASAAKI , MATAMIS GEORGE , ORIMOTO TAKASHI
发明人： KAI JAMES , PHAM TUAN , HIGASHITANI MASAAKI , MATAMIS GEORGE , ORIMOTO TAKASHI
IPC分类号： H01L21/8247 , H01L27/105 , H01L27/115
CPC分类号： H01L27/11529 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11536 , H01L27/11539
摘要： Non-volatile memory and integrated memory (480) and peripheral circuitry (490) fabrication processes are provided. Sets of charge storage regions (406, 408), such as NAND strings including multiple non- volatile storage elements, are formed over a semiconductor substrate (402) using a layer of charge storage material such as a first layer of polysilicon. An intermediate dielectric layer (404) is provided over the charge storage regions. A layer of conductive material such as a second layer of polysilicon is deposited over the substrate and etched to form the control gates (416, 418) for the charge storage regions and the gate regions (434) of the select transistors for the sets of storage elements. The first layer of polysilicon is removed from a portion of the substrate, facilitating fabrication of the select transistor gate regions from only the second layer of polysilicon. Peripheral circuitry formation is also incorporated into the fabrication process to form the gate regions for devices such as high voltage and logic transistors. The gate regions (444, 448) of these devices can be formed from the layer forming the control gates of the memory array.
摘要翻译：提供了非易失性存储器和集成存储器（480）和外围电路（490）制造工艺。使用诸如第一多晶硅层的电荷存储材料层，在半导体衬底（402）上形成电荷存储区（406,408），诸如包括多个非易失性存储元件的NAND串。中间电介质层（404）设置在电荷存储区域上方。将诸如第二多晶硅层的导电材料层沉积在衬底上并被蚀刻以形成用于电荷存储区域的控制栅极（416,418）和用于存储器组的选择晶体管的栅极区域（434）元素。从衬底的一部分去除第一层多晶硅，便于仅从第二层多晶硅制造选择晶体管栅极区。外围电路形成也被并入到制造过程中以形成诸如高电压和逻辑晶体管的器件的栅极区域。这些器件的栅极区域（444,448）可以由形成存储器阵列的控制栅极的层形成。

6. 发明申请

WO2012087820A3 NAND DEVICES HAVING A FLOATING GATE COMPRISING A FIN PORTION INTERDIGITATED WITH THE CONTROL GATE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：具有包括与控制门相互联系的熔融部分的浮动盖的浮动装置及其制造方法
公开(公告)号：WO2012087820A3
公开(公告)日：2012-08-16
申请号：PCT/US2011065472
申请日：2011-12-16
申请人： SANDISK TECHNOLOGIES INC , ALSMEIER JOHANN , PURAYATH VINOD , KAI JAMES , MATAMIS GEORGE
发明人： ALSMEIER JOHANN , PURAYATH VINOD , KAI JAMES , MATAMIS GEORGE
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L21/28273 , H01L27/11521 , H01L27/11524 , H01L29/66825 , H01L29/7881
摘要： A NAND device including a source, a drain and a channel located between the source and drain. The NAND device also includes a plurality of floating gates (110A) located over the channel and a plurality of electrically conducting fins (122). Each of the plurality of electrically conducting fins is located over one of the plurality of floating gates. The plurality of electrically conducting fins include a material other than polysilicon. The NAND device also includes a plurality of control gates (152,127). Each of the plurality of control gates is located adjacent to each of the plurality of floating gates and each of the plurality of electrically conducting fins.
摘要翻译：一种NAND器件，包括源极，漏极和位于源极和漏极之间的沟道。 NAND器件还包括位于通道上方的多个浮动栅极（110A）和多个导电翅片（122）。多个导电翅片中的每一个位于多个浮动栅极之一上。多个导电翅片包括多晶硅以外的材料。 NAND器件还包括多个控制栅极（152,127）。多个控制栅极中的每一个位于多个浮动栅极和多个导电散热片中的每一个附近。

7. 发明申请

WO2008089153A3 METHODS OF FORMING SPACER PATTERNS USING ASSIST LAYER FOR HIGH DENSITY SEMICONDUCTOR DEVICES 审中-公开
标题翻译：使用辅助层形成高密度半导体器件的间隔图案的方法
公开(公告)号：WO2008089153A3
公开(公告)日：2008-09-12
申请号：PCT/US2008051017
申请日：2008-01-14
申请人： SANDISK CORP , KAI JAMES , METAMIS GEORGE , PHAM TUAN DUC , HIGASHITANI MASAAKI , ORIMOTO TAKASHI
发明人： KAI JAMES , METAMIS GEORGE , PHAM TUAN DUC , HIGASHITANI MASAAKI , ORIMOTO TAKASHI
IPC分类号： H01L21/033 , H01L21/28 , H01L21/308 , H01L21/8247 , H01L27/115
CPC分类号： H01L21/28273 , H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L21/32139 , H01L27/115 , H01L27/11521
摘要： High density semiconductor devices and methods of fabricating the same are provided. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which in some instances are smaller than the smallest lithographically resolvable element size of the process being used. Spacers (620-634) are formed that serve as a mask, for etching one or more layers (604) beneath the spacers. An etch stop pad layer (608) having a material composition substantially similar to the spacer material is provided between a dielectric layer (606) and an insulating sacrificial layer such as silicon nitride. When etching the sacrificial layer, the matched pad layer provides an etch stop to avoid damaging and reducing the size of the dielectric layer. The matched material compositions further provide improved adhesion for the spacers, thereby improving the rigidity and integrity of the spacers.
摘要翻译：提供了高密度半导体器件及其制造方法。利用间隔制造技术来形成具有减小的特征尺寸的电路元件，其在一些情况下小于正在使用的工艺的最小可光刻可分辨的元件尺寸。形成用作掩模的隔板（620-634），用于蚀刻间隔物下面的一个或多个层（604）。具有与间隔物材料基本相似的材料组成的蚀刻停止衬垫层（608）设置在电介质层（606）和绝缘牺牲层（例如氮化硅）之间。当蚀刻牺牲层时，匹配的焊盘层提供蚀刻停止以避免损坏并减小电介质层的尺寸。匹配的材料组合物还提供了用于间隔物的改进的粘合性，从而提高了间隔物的刚度和完整性。

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