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1. 发明申请

WO2011146864A2 VIRTUAL INTERCONNECTION METHOD AND APPARATUS 审中-公开
标题翻译：虚拟互连方法和设备
公开(公告)号：WO2011146864A2
公开(公告)日：2011-11-24
申请号：PCT/US2011/037385
申请日：2011-05-20
申请人： INPA SYSTEMS, INC. , HUANG, Thomas B. , CHANG, Chioumin M. , TSAI, Huan-Chih , CHANG, Ting-Mao
发明人： HUANG, Thomas B. , CHANG, Chioumin M. , TSAI, Huan-Chih , CHANG, Ting-Mao
CPC分类号： G06F17/5027
摘要： A prototyping system includes (i) a vector processor having an interface for communicating with a host processor and a second interface (e.g., a vector processor bus) for dispatching vectors; (ii) a number of programmable logic circuit s each coupled to the second interface to receive the dispatched vectors; and (iii) a compiler for (a) partitioning an electronic circuit into multiple partitions, assigning each partition to one of the programmable logic circuits, (b) providing multiple connections each provided for connecting signals among the partitions, (c) providing in each programmable logic circuit an interface circuit module that manages the connections among partitions using a virtual interconnection technique, and (d) assigning the physical interconnection resources, such as pins of the programmable logic circuits and physical wires on the boards. First and further assigns at least one virtual interconnection (secondary I/O) between partitions to realize the connections among partitions. The prototyping system is associated with a method for prototyping an electronic design, which includes (i) compiling an electronic design into (a) multiple partitions, each partition being compiled for implementation in a programmable logic circuit (e.g., a field programmable gate array integrated circuit), and (b) multiple connections that connect signals between the partition; and (ii) compiling into each programmable logic circuit an interface circuit module for managing the connections using a virtual interconnection technique.
摘要翻译：原型系统包括（i）具有用于与主处理器通信的接口的矢量处理器和用于调度矢量的第二接口（例如，矢量处理器总线）; （ii）多个可编程逻辑电路，每个可编程逻辑电路都耦合到第二接口以接收调度向量; （iii）编译器，用于（a）将电子电路划分成多个分区，将每个分区分配给可编程逻辑电路之一，（b）提供多个连接，每个连接提供用于在分区之间连接信号;（c）可编程逻辑电路，使用虚拟互连技术管理分区之间的连接的接口电路模块，以及（d）分配诸如可编程逻辑电路的引脚和物理线的物理互连资源。首先进一步分配分区之间的至少一个虚拟互连（辅助I / O），以实现分区之间的连接。原型系统与用于原型设计电子设计的方法相关联，其包括（i）将电子设计编译为（a）多个分区，每个分区被编译用于在可编程逻辑电路中实现（例如，集成的现场可编程门阵列电路），和（b）连接分区之间的信号的多个连接; 和（ii）将每个可编程逻辑电路编译成用于使用虚拟互连技术来管理连接的接口电路模块。

2. 发明申请

WO2011146864A3 VIRTUAL INTERCONNECTION METHOD AND APPARATUS 审中-公开
标题翻译：虚拟互连方法和设备
公开(公告)号：WO2011146864A3
公开(公告)日：2012-02-23
申请号：PCT/US2011037385
申请日：2011-05-20
申请人： INPA SYSTEMS INC , HUANG THOMAS B , CHANG CHIOUMIN M , TSAI HUAN-CHIH , CHANG TING-MAO
发明人： HUANG THOMAS B , CHANG CHIOUMIN M , TSAI HUAN-CHIH , CHANG TING-MAO
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5027
摘要： A prototyping system includes (i) a vector processor having an interface for communicating with a host processor and a second interface (e.g., a vector processor bus) for dispatching vectors; (ii) a number of programmable logic circuit s each coupled to the second interface to receive the dispatched vectors; and (iii) a compiler for (a) partitioning an electronic circuit into multiple partitions, assigning each partition to one of the programmable logic circuits, (b) providing multiple connections each provided for connecting signals among the partitions, (c) providing in each programmable logic circuit an interface circuit module that manages the connections among partitions using a virtual interconnection technique, and (d) assigning the physical interconnection resources, such as pins of the programmable logic circuits and physical wires on the boards. First and further assigns at least one virtual interconnection (secondary I/O) between partitions to realize the connections among partitions. The prototyping system is associated with a method for prototyping an electronic design, which includes (i) compiling an electronic design into (a) multiple partitions, each partition being compiled for implementation in a programmable logic circuit (e.g., a field programmable gate array integrated circuit), and (b) multiple connections that connect signals between the partition; and (ii) compiling into each programmable logic circuit an interface circuit module for managing the connections using a virtual interconnection technique.
摘要翻译：原型系统包括（i）具有用于与主处理器通信的接口的矢量处理器和用于调度矢量的第二接口（例如，矢量处理器总线）; （ii）多个可编程逻辑电路，每个可编程逻辑电路都耦合到第二接口以接收调度向量; （iii）编译器，用于（a）将电子电路划分成多个分区，将每个分区分配给可编程逻辑电路之一，（b）提供多个连接，每个连接提供用于在分区之间连接信号;（c）可编程逻辑电路，使用虚拟互连技术管理分区之间的连接的接口电路模块，以及（d）分配诸如可编程逻辑电路的引脚和物理线的物理互连资源。首先进一步分配分区之间的至少一个虚拟互连（辅助I / O），以实现分区之间的连接。原型系统与用于原型设计电子设计的方法相关联，其包括（i）将电子设计编译为（a）多个分区，每个分区被编译用于在可编程逻辑电路中实现（例如，集成的现场可编程门阵列电路），和（b）连接分区之间的信号的多个连接; 和（ii）将每个可编程逻辑电路编译成用于使用虚拟互连技术来管理连接的接口电路模块。

3. 发明申请

WO2012012094A1 SCALABLE SYSTEM DEBUGGER FOR PROTOTYPE DEBUGGING 审中-公开
标题翻译：用于原型调试的可扩展系统调试器
公开(公告)号：WO2012012094A1
公开(公告)日：2012-01-26
申请号：PCT/US2011/041794
申请日：2011-06-24
申请人： INPA SYSTEMS, INC. , CHANG, Chioumin, M. , HUANG, Thomas, B. , TSAI, Huan-Chih , CHANG, Ting-Mao
发明人： CHANG, Chioumin, M. , HUANG, Thomas, B. , TSAI, Huan-Chih , CHANG, Ting-Mao
IPC分类号： G06F11/26 , G06F17/50
CPC分类号： G06F11/261
摘要： A prototype debugging system controlled by a host processor over a host bus includes: (a) a vector processor interface bus; (b) one or more programmable logic circuits, at least one of which provided to implement: (i) a logic circuit under verification; (ii) one or more programmable embedded debug circuits each receiving a first group of selected signals from the logic circuit under verification and providing control signals for (1) selecting a portion of the first group of selected signals, or (2) affecting the values of a second group of selected signals in the logic circuit under verification based on a portion of the first group of selected signals satisfying a predetermined triggering condition, wherein the programmable embedded debug circuits each including a built-in memory for storing signal vectors, the programmable embedded debug circuits each being configured according to a trigger specification defining one or more trigger states and triggering conditions; and (iii) a local debugging controller that controls programmable embedded debug circuits and transfers signal vectors between the built-in memories of the programmable embedded debug circuits and the vector processor interface bus; and (c) a vector processor which controls transferring of signal vectors between the host processor and the vector processor interface bus.
摘要翻译：由主处理器通过主机总线控制的原型调试系统包括：（a）向量处理器接口总线; （b）一个或多个可编程逻辑电路，其中至少一个被提供用于实现：（i）正在验证的逻辑电路; （ii）一个或多个可编程嵌入式调试电路，每个接收来自所述逻辑电路的第一组选定信号，并且提供用于（1）选择所述第一组选定信号的一部分的控制信号，或（2）影响所述值基于满足预定触发条件的所述第一组选择信号的一部分，所述逻辑电路中的所选逻辑电路中的第二组选择信号，其中所述可编程嵌入式调试电路各自包括用于存储信号向量的内置存储器，所述可编程嵌入式调试电路各自根据定义一个或多个触发状态和触发条件的触发规范进行配置; 和（iii）本地调试控制器，其控制可编程嵌入式调试电路并在可编程嵌入式调试电路的内置存储器和矢量处理器接口总线之间传送信号矢量; 以及（c）矢量处理器，其控制主处理器和矢量处理器接口总线之间的信号矢量的传送。

4. 发明申请

WO2010141512A1 METHOD AND APPARATUS FOR VERIFYING LOGIC CIRCUITS USING VECTOR EMULATION WITH VECTOR SUBSTITUTION 审中-公开
标题翻译：使用矢量仿真与矢量替换验证逻辑电路的方法和装置
公开(公告)号：WO2010141512A1
公开(公告)日：2010-12-09
申请号：PCT/US2010/036963
申请日：2010-06-01
申请人： INPA SYSTEMS, INC. , CHANG, Chioumin M. , HUANG, Thomas B. , TSAI, Huan-Chih , CHANG, Ting-Mao
发明人： CHANG, Chioumin M. , HUANG, Thomas B. , TSAI, Huan-Chih , CHANG, Ting-Mao
IPC分类号： G06F17/50
CPC分类号： G06F17/5027
摘要： A method for verifying a logic circuit in a prototyping system includes (a) configuring programmable logic circuits of the prototyping system to implement the logic circuit and to implement probe circuits for accessing internal nodes of the logic circuit; (b) preparing emulation vectors for use in a vector emulation of the logic circuit in the prototyping system; (c) setting one or more vector substitution points; (d) preparing one or more packet vectors at each vector substitution point for replacing emulation vectors in the vector emulation; (e) performing the vector emulation using the emulation vectors until one of the vector substitution points is reached; and (f) substituting packet vectors for the corresponding emulation vectors at vector substitution point and continuing the vector emulation.
摘要翻译：用于验证原型系统中的逻辑电路的方法包括（a）配置原型系统的可编程逻辑电路以实现逻辑电路并实现用于访问逻辑电路的内部节点的探测电路; （b）准备用于原型系统逻辑电路的矢量仿真中的仿真矢量; （c）设置一个或多个向量替换点; （d）在每个向量替换点处准备一个或多个分组向量以替换所述向量仿真中的仿真向量; （e）使用仿真矢量执行矢量仿真，直到达到矢量替代点之一; 和（f）在矢量替换点处将分组向量替换为对应的仿真矢量并继续矢量仿真。

5. 发明申请

WO2010047946A1 SNAPSHOT BASED EMULATION BY REPLAYING OF STORED INPUT SIGNALS IN A SELECTED TIME PERIOD 审中-公开
标题翻译：通过在选定的时间段内重新存储输入信号进行SNAPSHOT基础仿真
公开(公告)号：WO2010047946A1
公开(公告)日：2010-04-29
申请号：PCT/US2009/059728
申请日：2009-10-06
申请人： INPA SYSTEMS, INC. , CHANG, Chioumin M. , HUANG, Thomas B. , TSAI, Huan-Chih
发明人： CHANG, Chioumin M. , HUANG, Thomas B. , TSAI, Huan-Chih
IPC分类号： G06F17/50
CPC分类号： G06F17/5027
摘要： Using a vector-based emulation technique, a hardware-based prototyping system reduces time-consuming recompilation and reduces the iteration time for a verification run. The vector-based emulation technique takes advantage of information derived from user-defined probe points, automatically generated probe points and low-latency snapshots. Using a bounded-cycle simulation technique, the hardware-based prototyping system can provide complete or partial simulation traces covering interested signals and can efficiently evaluates assertions. A user is therefore able to debug in a real system test and to identify causes of fault conditions interactively under a controlled vector debugging environment.
摘要翻译：使用基于向量的仿真技术，基于硬件的原型系统可以减少耗时的重新编译，并减少验证运行的迭代时间。基于矢量的仿真技术利用从用户定义的探测点，自动生成的探测点和低延迟快照得到的信息。使用有界循环模拟技术，基于硬件的原型系统可以提供涵盖感兴趣信号的完整或部分模拟轨迹，并可以有效地评估断言。因此，用户能够在真实的系统测试中进行调试，并在受控的向量调试环境下交互地识别故障条件的原因。

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