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1. 发明申请

WO2004059651A3 NONVOLATILE MEMORY UNIT WITH SPECIFIC CACHE 审中-公开
公开(公告)号：WO2004059651A3
公开(公告)日：2004-07-15
申请号：PCT/IB2002/005615
申请日：2002-12-27
申请人： SOLID STATE SYSTEM CO., LTD. , WANG, Chih-Hung , KUO, Chun-Hao , LIN, Chun-Hung
发明人： WANG, Chih-Hung , KUO, Chun-Hao , LIN, Chun-Hung
IPC分类号： G06F12/08
摘要： The invention provides a method for organizing a writing operation to a nonvolatile memory. The method comprises setting a specific cache area, into which a specific data belonging to specific group ,of logical blocs is to be written. it is determined whether , or not the writing operation is a random write. If the writing operation is the random write, then the following steps are performed: determining whether or not the writing operation is to write a data that is belonging to the specific group of logical blocks; and writing the data into the specific cache area if the data is belonging to the specific group of logical blocks. As a result, a swap action between a data block and a writing block can be avoided during a random write operation. A storage structure in a nonvolatile memory device are organized to perform the forgoing writing operation.

2. 发明申请

WO2004019409A1 COMPACT MASK PROGRAMMABLE ROM 审中-公开
标题翻译：紧凑的可编程ROM
公开(公告)号：WO2004019409A1
公开(公告)日：2004-03-04
申请号：PCT/IB2002/003454
申请日：2002-08-26
申请人： SOLID STATE SYSTEM CO., LTD. , LIOU, Jhyy-Cheng , LIN, Chin-Hsi
发明人： LIOU, Jhyy-Cheng , LIN, Chin-Hsi
IPC分类号： H01L27/115
CPC分类号： H01L27/11233 , G11C17/12 , H01L27/105 , H01L27/112 , H01L27/11226 , H01L27/1126 , H01L27/11293
摘要： A compact mask programmable read-only memory (Mask ROM) is described, comprising a plurality of word lines, a plurality ofbit lines, and a plurality ofMOS-type and diffusion-type memory cells arranged in an array. The memory cells in one column are coupled to one bit line, and the gates of the MOS-type cells in one row are coupled to one word line via contacts, wherein two columns of memory cells share a column of contacts. A MOS-type cell shares its source and drain with two memory cells in the same column, and a diffusion-type cell directly connects with the diffusions of two adjacent memory cells. A constant number of continuous memory cells are grouped as a memory string, wherein the two diffusions of the two terminal memory cells are electrically connected to a bank select transistor and a ground line, respectively.
摘要翻译：描述了紧凑的掩模可编程只读存储器（掩模ROM），其包括多个字线，多个位线以及排列成阵列的多个MOS型和扩散型存储单元。一列中的存储单元耦合到一个位线，并且一行中的MOS型单元的栅极经由触点耦合到一个字线，其中两列存储器单元共享一列触点。 MOS型电池与同一列中的两个存储单元共用其源极和漏极，扩散型单元与两个相邻存储单元的扩散直接连接。恒定数量的连续存储器单元被分组为存储器串，其中两个端子存储单元的两个扩散分别电连接到存储体选择晶体管和接地线。

3. 发明申请

WO2004097835A2 NONVOLATILE MEMORY STRUCTURE WITH HIGH SPEED HIGH BANDWIDTH AND LOW VOLTAGE 审中-公开
标题翻译：具有高速高带宽和低电压的非易失性存储器结构
公开(公告)号：WO2004097835A2
公开(公告)日：2004-11-11
申请号：PCT/IB0301594
申请日：2003-04-28
申请人： SOLID STATE SYSTEM CO LTD , LIN CHIN-HSI
发明人： LIN CHIN-HSI
IPC分类号： G11C20060101 , G11C7/00 , G11C
CPC分类号： G11C7/1039 , G11C7/18 , G11C7/22 , G11C16/28 , G11C17/12 , G11C17/123 , G11C2207/002
摘要： A layout of a nonvolatile memory structure has multiple memory array banks and multiple double-ended sense amplifiers. Each of the double-ended sense amplifiers is implemented between two of the memory array banks for sharing use, wherein when one array bank is decoded, the other one array bank serving as a reference array. Wherein, every two of the memory array banks are grouped in one dual bank, and one of the double-ended sense amplifiers is implemented in the dual bank. Alternatively, a predetermined number of the memory array banks are grouped into one bank unit for multiple bank units, and one of the double-ended sense amplifiers is implemented between two of the bank units.
摘要翻译：非易失性存储器结构的布局具有多个存储器阵列组和多个双端读出放大器。每个双端读出放大器被实现在用于共享使用的两个存储器阵列组之间，其中当一个阵列组被解码时，另一个阵列组用作参考阵列。其中，每两个存储器阵列组被分组在一个双组中，并且双端读出放大器中的一个在双行中实现。或者，预定数量的存储器阵列组被分组为多个存储体单元的一个存储单元，并且双端读出放大器中的一个在两个存储体单元之间实现。

4. 发明申请

WO2004059651A2 NONVOLATILE MEMORY UNIT WITH SPECIFIC CACHE 审中-公开
标题翻译：具有特殊缓存的非易失性存储单元
公开(公告)号：WO2004059651A2
公开(公告)日：2004-07-15
申请号：PCT/IB0205615
申请日：2002-12-27
申请人： SOLID STATE SYSTEM CO LTD , WANG CHIH-HUNG , KUO CHUN-HAO , LIN CHUN-HUNG
发明人： WANG CHIH-HUNG , KUO CHUN-HAO , LIN CHUN-HUNG
IPC分类号： G06F3/06 , G06F12/02 , G06F12/08 , G11C20060101 , G11C
CPC分类号： G06F12/0246 , G06F3/0613 , G06F3/064 , G06F3/0679 , G06F12/0875 , G06F2212/7203 , G06F2212/7207
摘要： The invention provides a method for organizing a writing operation to a nonvolatile memory. The method comprises setting a specific cache area, into which a specific data belonging to specific group ,of logical blocs is to be written. it is determined whether , or not the writing operation is a random write. If the writing operation is the random write, then the following steps are performed: determining whether or not the writing operation is to write a data that is belonging to the specific group of logical blocks; and writing the data into the specific cache area if the data is belonging to the specific group of logical blocks. As a result, a swap action between a data block and a writing block can be avoided during a random write operation. A storage structure in a nonvolatile memory device are organized to perform the forgoing writing operation.
摘要翻译：本发明提供一种用于组织对非易失性存储器的写入操作的方法。该方法包括设置要写入逻辑组的属于特定组的特定数据的特定缓存区域。确定写入操作是否是随机写入。如果写入操作是随机写入，则执行以下步骤：确定写入操作是否写入属于特定组逻辑块的数据; 并且如果数据属于特定的逻辑块组，则将数据写入特定高速缓存区域。结果，在随机写入操作期间可以避免数据块和写入块之间的交换动作。组织非易失性存储装置中的存储结构以执行正在进行的写入操作。

5. 发明申请

WO2004097835A3 NONVOLATILE MEMORY STRUCTURE WITH HIGH SPEED HIGH BANDWIDTH AND LOW VOLTAGE 审中-公开
公开(公告)号：WO2004097835A3
公开(公告)日：2004-11-11
申请号：PCT/IB2003/001594
申请日：2003-04-28
申请人： SOLID STATE SYSTEM CO., LTD. , LIN, Chin-Hsi
发明人： LIN, Chin-Hsi
IPC分类号： G11C11/4091
摘要： A layout of a nonvolatile memory structure has multiple memory array banks and multiple double-ended sense amplifiers. Each of the double-ended sense amplifiers is implemented between two of the memory array banks for sharing use, wherein when one array bank is decoded, the other one array bank serving as a reference array. Wherein, every two of the memory array banks are grouped in one dual bank, and one of the double-ended sense amplifiers is implemented in the dual bank. Alternatively, a predetermined number of the memory array banks are grouped into one bank unit for multiple bank units, and one of the double-ended sense amplifiers is implemented between two of the bank units.

6. 发明申请

WO2004019372A3 CONTACTLESS MASK PROGRAMMABLE ROM 审中-公开
标题翻译：无缝可编程ROM
公开(公告)号：WO2004019372A3
公开(公告)日：2004-06-03
申请号：PCT/IB0301596
申请日：2003-04-28
申请人： SOLID STATE SYSTEM CO LTD , LIOU JHYY-CHENG , LIN CHIN-HSI
发明人： LIOU JHYY-CHENG , LIN CHIN-HSI
IPC分类号： H01L20060101 , H01L21/8238 , H01L21/8246 , H01L21/8247 , H01L27/112 , H01L27/115 , H01L29/76
CPC分类号： H01L27/11233 , H01L27/112 , H01L27/11226 , H01L27/1126
摘要： A contactless Mask ROM is described, comprising a plurality of MOS-type memory cells. The memory cells include a plurality of first memory cells and a plurality of second memory cells. The first memory cells have a first channel conductivity so that they are depletion-mode MOS transistors, and the second memory cells have a second channel conductivity so that they are enhanced-mode MOS transistors. In the contactless Mask ROM, a memory cell shares two diffusions with two adjacent memory cells that are aligned with the memory cell along a first direction.
摘要翻译：描述了一种非接触式掩模ROM，包括多个MOS型存储单元。存储单元包括多个第一存储单元和多个第二存储单元。第一存储单元具有第一通道导电性，使得它们是耗尽型MOS晶体管，并且第二存储单元具有第二沟道电导率，使得它们是增强型MOS晶体管。在非接触式掩模ROM中，存储器单元与沿着第一方向与存储器单元对准的两个相邻的存储器单元共享两个扩散。

7. 发明申请

WO2004019408A1 CONTACTLESS MASK PROGRAMMABLE ROM 审中-公开
标题翻译：无缝可编程ROM
公开(公告)号：WO2004019408A1
公开(公告)日：2004-03-04
申请号：PCT/IB2002/003451
申请日：2002-08-26
申请人： SOLID STATE SYSTEM CO., LTD. , LIOU, Jhyy-Cheng , LIN, Chin-Hsi
发明人： LIOU, Jhyy-Cheng , LIN, Chin-Hsi
IPC分类号： H01L27/115
CPC分类号： H01L27/11233 , H01L27/112 , H01L27/11226 , H01L27/1126
摘要： A contactless mask programmable read-only memory (Mask ROM) is described, comprising a plurality of word lines extending in row direction and a plurality of diffusions arranged in rows and columns in a substrate. In the Mask ROM, two rows of diffusions are separated by a word line. Two adjacent diffusions in the same column, the word line between the two diffusions, and the substrate between the two diffusions together constitute a memory cell. The memory cells include a plurality of first memory cells and a plurality of second memory cells. The channel length, the gate oxide width or the channel dopant concentration of the fIrst memory cells is different from that of the second memory cells, such that the threshold voltage of the fIrst memory cells is substantially different from that of the second memory cells.
摘要翻译：描述了一种非接触屏蔽可编程只读存储器（Mask ROM），其包括沿行方向延伸的多个字线和在衬底中以行和列布置的多个扩散。在掩模ROM中，两行扩散由字线分开。同一列中的两个相邻扩散，两个扩散之间的字线和两个扩散之间的衬底一起构成存储器单元。存储单元包括多个第一存储单元和多个第二存储单元。第一存储器单元的沟道长度，栅极氧化物宽度或沟道掺杂剂浓度与第二存储单元的沟道长度，沟道掺杂浓度不同，使得第一存储单元的阈值电压与第二存储单元的阈值电压基本不同。

8. 发明申请

WO2004019372A2 CONTACTLESS MASK PROGRAMMABLE ROM 审中-公开
标题翻译：非接触式面具可编程ROM
公开(公告)号：WO2004019372A2
公开(公告)日：2004-03-04
申请号：PCT/IB2003/001596
申请日：2003-04-28
申请人： SOLID STATE SYSTEM CO., LTD. , LIOU, Jhyy-Cheng , LIN, Chin-Hsi
发明人： LIOU, Jhyy-Cheng , LIN, Chin-Hsi
IPC分类号： H01L
CPC分类号： H01L27/11233 , H01L27/112 , H01L27/11226 , H01L27/1126
摘要： A contactless Mask ROM is described, comprising a plurality of MOS-type memory cells. The memory cells include a plurality of first memory cells and a plurality of second memory cells. The first memory cells have a first channel conductivity so that they are depletion-mode MOS transistors, and the second memory cells have a second channel conductivity so that they are enhanced-mode MOS transistors. In the contactless Mask ROM, a memory cell shares two diffusions with two adjacent memory cells that are aligned with the memory cell along a first direction.
摘要翻译：描述了一种非接触式掩模ROM，其包括多个MOS型存储单元。存储器单元包括多个第一存储器单元和多个第二存储器单元。第一存储单元具有第一沟道导电性，使得它们是耗尽型MOS晶体管，并且第二存储单元具有第二沟道导电性，使得它们是增强型MOS晶体管。在非接触掩模ROM中，存储单元与沿着第一方向与存储单元对准的两个相邻存储单元共享两个扩散。

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