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1. 发明申请

WO2012177368A1 BIT SCAN CIRCUIT AND METHOD IN NON-VOLATILE MEMORY 审中-公开
标题翻译：非易失性存储器中的位扫描电路和方法
公开(公告)号：WO2012177368A1
公开(公告)日：2012-12-27
申请号：PCT/US2012/040145
申请日：2012-05-31
申请人： SANDISK TECHNOLOGIES INC. , LIU, Bo , PARK, Jongmin , CHEN, Chen , KUO, Tien-Chien
发明人： LIU, Bo , PARK, Jongmin , CHEN, Chen , KUO, Tien-Chien
IPC分类号： G11C29/40 , G11C29/44
CPC分类号： G11C29/40 , G11C29/44
摘要： A circuit (150) for counting in an N-bit string (10) a number of bits M, having a first binary value includes N latch circuits in a daisy chain (100) where each latch circuit has a tag bit that controls each to be either in a no-pass or pass state. Initially the tag bits are set according to the bits of the N-bit string where the first binary value corresponds to a no-pass state. A clock signal having a pulse train is run through the daisy chain to "interrogate" any no-pass latch circuits. It races right through any pass latch circuit. However, for a no-pass latch circuit, a leading pulse while being blocked also resets after a pulse period the tag bit from "no-pass" to "pass" state to allow subsequent pulses to pass. After all no-pass latch circuits have been reset, M is given by the number of missing pulses from the pulse train.
摘要翻译：用于以N位串（10）计数具有第一二进制值的位M的电路（150）包括菊花链（100）中的N个锁存电路，其中每个锁存电路具有一个标签位，要么是没有通过，要么是通过状态。最初，标签位根据N位串的位进行设置，其中第一个二进制值对应于无通状态。具有脉冲串的时钟信号通过菊花链运行以“询问”任何无通路锁存电路。它可以通过任何通过锁存电路进行比赛。然而，对于无通路锁存电路，被阻塞的前导脉冲也在标签位从“无通”状态到“通过”状态的脉冲周期之后复位，以允许随后的脉冲通过。在所有无通路锁存电路复位之后，M由脉冲序列的丢失脉冲数给出。

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