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1. 发明申请

WO2013155049A1 BREAK-AWAY SWITCH ACTUATED TRAILER LIGHTING AND BRAKING SYSTEM 审中-公开
标题翻译：断开开关动作拖拉机照明和制动系统
公开(公告)号：WO2013155049A1
公开(公告)日：2013-10-17
申请号：PCT/US2013/035739
申请日：2013-04-09
申请人： MCCOLLUM, John
发明人： MCCOLLUM, John
IPC分类号： B60T7/20 , B60T8/17 , B60T17/18
CPC分类号： B60Q11/00 , B60Q1/305 , B60Q1/46 , B60T7/20 , B60T17/22
摘要： A system for operating alarm features of a trailer towed by a tractor in the event of unintended decoupling of the trailer from the tractor. The system may include a breakaway switch or its functional equivalent, a flasher, and a source of emergency power such as a battery. The output of the system may operate only lights though the flasher, or optionally, also at least one electric brake of the trailer. Where braking is provided, the supply of electrical power is uninterrupted as by the flasher. Importantly, an anti-feedback feature prevents unintended operation of the lights and brake due to back- feeding from the electrical system of the tractor under ordinary operating conditions.
摘要翻译：如果拖车与拖拉机意外脱钩，则用于操作由拖拉机牵引的拖车的报警功能的系统。该系统可以包括分离开关或其功能等效物，闪光器和诸如电池的应急电源。系统的输出可以仅通过闪光灯或者可选地还可以是拖车的至少一个电动制动器操作灯。在提供制动的情况下，电源的供电与闪光灯不间断。重要的是，防反馈功能可防止在正常工作条件下由于拖拉机的电气系统的反馈而导致灯和制动器的意外操作。

2. 发明申请

WO2006138086A3 NON-VOLATILE TWO-TRANSISTOR PROGRAMMABLE LOGIC CELL AND ARRAY LAYOUT 审中-公开
公开(公告)号：WO2006138086A3
公开(公告)日：2006-12-28
申请号：PCT/US2006/021569
申请日：2006-06-01
申请人： ACTEL CORPORATION , DHAOUI, Fethi , MCCOLLUM, John , BELLIPPADY, Vidyadhara , WANG, Zhigang
发明人： DHAOUI, Fethi , MCCOLLUM, John , BELLIPPADY, Vidyadhara , WANG, Zhigang
IPC分类号： H01L29/788
摘要： A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch- transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.

3. 发明申请

WO2005034175A3 PROGRAMMABLE SYSTEM ON A CHIP 审中-公开
标题翻译：芯片可编程系统
公开(公告)号：WO2005034175A3
公开(公告)日：2005-12-15
申请号：PCT/US2004024362
申请日：2004-07-28
申请人： ACTEL CORP , BAKKER GREGORY , EL-AYAT KHALED , SPEERS THEODORE , ZHU LIMIN , SCHUBERT BRIAN , BALASUBRAMANIAN RABINDRANATH , KOLKIND KURT , BARRAZA THOMAS F , NARAYANAN VENKATESH , MCCOLLUM JOHN , PLANTS WILLIAM C
发明人： BAKKER GREGORY , EL-AYAT KHALED , SPEERS THEODORE , ZHU LIMIN , SCHUBERT BRIAN , BALASUBRAMANIAN RABINDRANATH , KOLKIND KURT , BARRAZA THOMAS F , NARAYANAN VENKATESH , MCCOLLUM JOHN , PLANTS WILLIAM C
IPC分类号： H01L20060101 , H03K19/177
CPC分类号： H03K19/1776 , G01K7/015 , G06F1/08 , G06F1/28 , G06F1/30 , G06F15/7842 , G06F15/7867 , H03F3/45475 , H03F2203/45136 , H03F2203/45166 , H03K17/223 , H03K19/177 , H03K19/17732
摘要： A programmable system-on-a-chip integrated circuit device comprises a programmable logic block (12), a non-volatile memory block (14), an analog sub-system (16), an analog input/output circuit block (22), and a digital input/output circuit block 20. A programmable interconnect architecture (Fig. 2) includes programmable elements and interconnect conductors. Ones of the programmable elements are coupled to the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, the digital input/output circuit block, and to the interconnect conductors, such that inputs and outputs of the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, and the digital input/output circuit block can be programmably coupled to one another.
摘要翻译：一种可编程片上系统集成电路装置，包括可编程逻辑块（12），非易失性存储块（14），模拟子系统（16），模拟输入/输出电路块（22）和数字输入/输出电路块20.可编程互连架构（图2）包括可编程元件和互连导体。可编程元件的一部分耦合到可编程逻辑块，非易失性存储器块，模拟子系统，模拟输入/输出电路块，数字输入/输出电路块和互连导体，使得可编程逻辑块，非易失性存储器块，模拟子系统，模拟输入/输出电路块和数字输入/输出电路块的输入和输出可以可编程地彼此耦合。

4. 发明申请

WO2005081976A3 REPROGRAMMABLE METAL-TO-METAL ANTIFUSE EMPLOYING CARBON-CONTAINING ANTIFUSE MATERIAL 审中-公开
公开(公告)号：WO2005081976A3
公开(公告)日：2005-09-09
申请号：PCT/US2005/005749
申请日：2005-02-22
申请人： ACTEL CORPORATION , ISSAQ, A., Farid , HAWLEY, Frank , MCCOLLUM, John
发明人： ISSAQ, A., Farid , HAWLEY, Frank , MCCOLLUM, John
IPC分类号： H01L31/0256
摘要： A reprogrammable metal-to-metal antifuse is disposed between two metal interconnect layers in an integrated circuit. A lower barrier layer is formed from Ti. A lower adhesion-promoting layer is disposed over the lower Ti barrier layer. An antifuse material layer selected from a group comprising at least one of amorphous carbon and amorphous carbon doped with at least one of hydrogen and fluorine is disposed over the lower adhesion-promoting layer. An upper adhesion-promoting layer is disposed over the antifuse material layer. An upper Ti barrier layer is disposed over the upper adhesion-promoting layer.

5. 发明申请

WO2005067497A2 RADIATION TOLERANT SRAM BIT 审中-公开
标题翻译：辐射稳定SRAM位
公开(公告)号：WO2005067497A2
公开(公告)日：2005-07-28
申请号：PCT/US2004/043631
申请日：2004-12-28
申请人： ACTEL CORPORATION , MCCOLLUM, John
发明人： MCCOLLUM, John
IPC分类号： G06F11/00 , G11C5/00 , G11C11/412
CPC分类号： G11C11/4125 , G11C5/005
摘要： In an integrated circuit, a radiation tolerant static random access memory device comprising a first inverter having an input and an output, a second inverter having an input and an output. A first resistor is coupled between the output of the first inverter and the input of the second inverter. A second resistor is coupled between the output of the second inverter and the input of the first inverter. A first write transistor is coupled to the output of the first inverter and has a gate coupled to a source of a first set of write-control signals and a second write transistor is coupled to the output of the second inverter and has a gate coupled to said source of a second set of write-control signals. Finally, a pass transistor has a gate coupled to the output of on of the first and second inverters.
摘要翻译：在集成电路中，包括具有输入和输出的第一反相器的辐射耐受静态随机存取存储器件，具有输入和输出的第二反相器。第一电阻器耦合在第一反相器的输出端和第二反相器的输入端之间。第二电阻耦合在第二反相器的输出端和第一反相器的输入端之间。第一写入晶体管耦合到第一反相器的输出，并且具有耦合到第一组写入控制信号的源的栅极，并且第二写入晶体管耦合到第二反相器的输出，并且具有耦合到所述源的第二组写控制信号。最后，传输晶体管具有耦合到第一和第二反相器的输出的栅极。

6. 发明申请

WO2005081976A2 REPROGRAMMABLE METAL-TO-METAL ANTIFUSE EMPLOYING CARBON-CONTAINING ANTIFUSE MATERIAL 审中-公开
标题翻译：使用含碳的抗菌材料的可复制金属至金属抗体
公开(公告)号：WO2005081976A2
公开(公告)日：2005-09-09
申请号：PCT/US2005005749
申请日：2005-02-22
申请人： ACTEL CORP , ISSAQ A FARID , HAWLEY FRANK , MCCOLLUM JOHN
发明人： ISSAQ A FARID , HAWLEY FRANK , MCCOLLUM JOHN
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A reprogrammable metal-to-metal antifuse is disposed between two metal interconnect layers in an integrated circuit. A lower barrier layer is formed from Ti. A lower adhesion-promoting layer is disposed over the lower Ti barrier layer. An antifuse material layer selected from a group comprising at least one of amorphous carbon and amorphous carbon doped with at least one of hydrogen and fluorine is disposed over the lower adhesion-promoting layer. An upper adhesion-promoting layer is disposed over the antifuse material layer. An upper Ti barrier layer is disposed over the upper adhesion-promoting layer.
摘要翻译：在集成电路中的两个金属互连层之间设置可再编程的金属对金属反熔丝。由Ti形成下阻挡层。下部粘附促进层设置在下部Ti阻挡层上。选自包含至少一种无定形碳和掺杂有氢和氟中的至少一种的无定形碳的反熔丝材料层设置在下部粘附促进层上。上部粘合促进层设置在反熔丝材料层上。在上部粘合促进层上设置上部Ti阻挡层。

7. 发明申请

WO2005010889A1 FLASH/DYNAMIC RANDOM ACCESS MEMORY FIELD PROGRAMMABLE GATE ARRAY 审中-公开
标题翻译：闪存/动态随机存取现场可编程门阵列
公开(公告)号：WO2005010889A1
公开(公告)日：2005-02-03
申请号：PCT/US2004/022556
申请日：2004-07-13
申请人： ACTEL CORPORATION , MCCOLLUM, John , BELLIPPADY, Vidya , BAKKER, Gregory
发明人： MCCOLLUM, John , BELLIPPADY, Vidya , BAKKER, Gregory
IPC分类号： G11C7/00
CPC分类号： G11C11/406
摘要： A circuit for selectively interconnecting two nodes in an integrated circuit device includes a memory array having a plurality of wordlines and a plurality of bitlines. A refresh transistor has a source coupled to one of the plurality of bitlines, a control gate coupled to a dynamic random access memory wordline and a drain. A switching transistor has a gate coupled to the drain of the refresh transistor, a source coupled to a first one of the nodes and a drain coupled to a second one of the nodes. An address decoder for supplies periodic signals to the wordlines and the dynamic random access memory wordline.
摘要翻译：用于选择性地互连集成电路器件中的两个节点的电路包括具有多个字线和多个位线的存储器阵列。刷新晶体管具有耦合到多个位线之一的源极，耦合到动态随机存取存储器字线和漏极的控制栅极。开关晶体管具有耦合到刷新晶体管的漏极的栅极，耦合到节点中的第一节点的源极和耦合到节点中的第二节点的漏极。地址解码器，用于向字线和动态随机存取存储器字线提供周期性信号。

8. 发明申请

WO2006138086A2 NON-VOLATILE TWO-TRANSISTOR PROGRAMMABLE LOGIC CELL AND ARRAY LAYOUT 审中-公开
标题翻译：非易失性双向晶体管可编程逻辑单元和阵列布局
公开(公告)号：WO2006138086A2
公开(公告)日：2006-12-28
申请号：PCT/US2006021569
申请日：2006-06-01
申请人： ACTEL CORP , DHAOUI FETHI , MCCOLLUM JOHN , BELLIPPADY VIDYADHARA , WANG ZHIGANG
发明人： DHAOUI FETHI , MCCOLLUM JOHN , BELLIPPADY VIDYADHARA , WANG ZHIGANG
IPC分类号： H01L29/788
CPC分类号： H01L27/0203 , H01L21/823493 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch- transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.
摘要翻译：在半导体本体中形成双晶体管非易失性存储单元。记忆晶体管阱设置在半导体本体内。开关晶体管阱设置在半导体本体内并且与存储晶体管良好地电隔离。包括间隔开的源极和漏极区域的存储晶体管形成在存储器晶体管阱内。在开关晶体管阱区内形成包括间隔开的源极和漏极区的开关晶体管。浮置栅极与存储晶体管和开关晶体管的源极和漏极区域绝缘并自对准。控制栅极设置在浮置栅极之上并与存储晶体管的源极和漏极区域以及开关晶体管对准。

9. 发明申请

WO2005081976A9 REPROGRAMMABLE METAL-TO-METAL ANTIFUSE EMPLOYING CARBON-CONTAINING ANTIFUSE MATERIAL 审中-公开
标题翻译：使用含碳的抗腐蚀材料的可再生金属 - 金属抗菌剂
公开(公告)号：WO2005081976A9
公开(公告)日：2006-08-24
申请号：PCT/US2005005749
申请日：2005-02-22
申请人： ACTEL CORP , ISSAQ A FARID , HAWLEY FRANK , MCCOLLUM JOHN
发明人： ISSAQ A FARID , HAWLEY FRANK , MCCOLLUM JOHN
IPC分类号： H01L31/0256 , H01L23/48 , H01L29/00 , H01L31/0312
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A reprogrammable metal-to-metal antifuse is disposed between two metal interconnect layers in an integrated circuit. A lower barrier layer is formed from Ti. A lower adhesion-promoting layer is disposed over the lower Ti barrier layer. An antifuse material layer selected from a group comprising at least one of amorphous carbon and amorphous carbon doped with at least one of hydrogen and fluorine is disposed over the lower adhesion-promoting layer. An upper adhesion-promoting layer is disposed over the antifuse material layer. An upper Ti barrier layer is disposed over the upper adhesion-promoting layer.
摘要翻译：在集成电路中的两个金属互连层之间设置可重新编程的金属 - 金属反熔丝。下阻挡层由Ti形成。下部助粘剂层设置在下部钛阻挡层上。选自包括无定形碳和掺杂有氢和氟中的至少一种的无定形碳中的至少一种的抗熔材料层设置在下粘合促进层上。在反熔丝材料层上设置有上部增粘层。上部Ti阻挡层设置在上部粘合促进层上。

10. 发明申请

WO2005067497A3 RADIATION TOLERANT SRAM BIT 审中-公开
标题翻译：辐射稳定SRAM位
公开(公告)号：WO2005067497A3
公开(公告)日：2006-06-29
申请号：PCT/US2004043631
申请日：2004-12-28
申请人： ACTEL CORP , MCCOLLUM JOHN
发明人： MCCOLLUM JOHN
IPC分类号： G11C11/00 , G06F11/00 , G11C5/00 , G11C11/412
CPC分类号： G11C11/4125 , G11C5/005
摘要： In an integrated circuit, a radiation tolerant static random access memory device comprising a first inverter having an input and an output, a second inverter having an input and an output. A first resistor is coupled between the output of the first inverter and the input of the second inverter. A second resistor is coupled between the output of the second inverter and the input of the first inverter. A first write transistor is coupled to the output of the first inverter and has a gate coupled to a source of a first set of write-control signals and a second write transistor is coupled to the output of the second inverter and has a gate coupled to said source of a second set of write-control signals. Finally, a pass transistor has a gate coupled to the output of on of the first and second inverters.
摘要翻译：在集成电路中，包括具有输入和输出的第一反相器的辐射耐受静态随机存取存储器件，具有输入和输出的第二反相器。第一电阻器耦合在第一反相器的输出端和第二反相器的输入端之间。第二电阻耦合在第二反相器的输出端和第一反相器的输入端之间。第一写入晶体管耦合到第一反相器的输出，并且具有耦合到第一组写入控制信号的源的栅极，并且第二写入晶体管耦合到第二反相器的输出，并且具有耦合到所述源的第二组写控制信号。最后，传输晶体管具有耦合到第一和第二反相器的输出的栅极。

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