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1. 发明授权

US10863148B2 Tile-selection based deep demosaicing acceleration 有权
公开(公告)号：US10863148B2
公开(公告)日：2020-12-08
申请号：US16010313
申请日：2018-06-15
申请人： QUALCOMM Incorporated
发明人： Shang-Chih Chuang , Xiaoyun Jiang , Jun Zuo Liu
IPC分类号： H04N9/45 , H04N9/04 , H04N5/357 , G06T3/40 , G06T5/00 , H04N9/64
摘要： Aspects of the present disclosure relate to systems and methods for selectively processing tiles of a captured image. The captured image may be parsed into a plurality of tiles. A subset of the plurality of tiles may be selected based at least in part on at least one metric. The selected tiles may be processed according to a first technique, while each unselected tile may be selectively processed according to one or more techniques different from the first technique. The first technique and the one or more techniques may each be either an image demosaicing technique or an image denoising technique.

2. 发明授权

US10194080B2 Multiple channel imaging system 有权
公开(公告)号：US10194080B2
公开(公告)日：2019-01-29
申请号：US14877681
申请日：2015-10-07
申请人： Sensors Unlimited, Inc.
发明人： Robert Rozploch
IPC分类号： H04N9/45 , G06K9/20 , G06K9/32 , H04N5/232 , H04N5/225 , H04N5/33 , H04N5/247
摘要： A method of imaging includes monitoring a field of view with a first imaging sensor of a multiple channel imaging system and activating a second component of the imaging system from a stand by state to an active state upon detection of a change in the field of view of the first imaging sensor. The second component can include a second imaging sensor. The second imaging sensor can have a field of view overlapping with the field of view of the first imaging sensor. The first imaging sensor can be configured for imaging in a first spectral range, wherein the second imaging sensor is configured for imaging in a second spectral range that is different from the first spectral range. The first and second spectral ranges can be overlapping or non-overlapping.

3. 发明授权

US10097799B2 Image sensor device with macropixel processing and related devices and methods 有权
公开(公告)号：US10097799B2
公开(公告)日：2018-10-09
申请号：US15958244
申请日：2018-04-20
申请人： STMicroelectronics International N.V.
发明人： Mahesh Chandra , Brejesh Lall
IPC分类号： H04N9/45 , H04N5/347 , H04N9/04
摘要： An image sensor device may include an array of image sensing pixels with adjacent image sensing pixels being arranged in macropixel, and a processor coupled to the array of image sensing pixels. The processor may be configured to receive pixel signals from the array of image sensing pixels, and arrange the received pixel signals into macropixel signal sets for respective macropixels. The processor may be configured to perform, in parallel, an image enhancement operation on the received pixel signals for each macropixel signal set to generate enhanced macropixel signals, and transmit the enhanced macropixel signals.

4. 发明授权

US09575665B2 Graphics display system with unified memory architecture 有权
标题翻译：图形显示系统具有统一的内存架构
公开(公告)号：US09575665B2
公开(公告)日：2017-02-21
申请号：US14790923
申请日：2015-07-02
申请人： Broadcom Corporation
发明人： Alexander G. MacInnis , Chengfuh Tang , Xiaodong Xie , James T. Patterson , Greg A. Kranawetter
IPC分类号： G06F3/00 , G06F3/06 , G06T1/60 , G06T1/20 , G06T9/00 , G09G5/00 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/34 , G09G5/36 , H04N5/04 , H04N5/14 , H04N5/445 , H04N5/45 , H04N7/01 , H04N9/45 , H04N9/64 , H04N21/422 , H04N21/426 , H04N21/43 , H04N21/431 , H04N21/434 , H04N21/4402 , H04N21/443 , H04N21/47 , H04N19/61 , H04N19/44 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/59 , G09G5/02 , H04N5/12 , H04N5/44 , H04N5/46 , H04N11/14 , H04N11/20
CPC分类号： G06F3/0611 , G06F3/0653 , G06F3/0659 , G06F3/0683 , G06T1/20 , G06T1/60 , G06T9/00 , G06T9/007 , G09G5/001 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G5/363 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/126 , G09G2360/128 , H04N5/04 , H04N5/126 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/44591 , H04N5/45 , H04N5/46 , H04N7/0122 , H04N7/0135 , H04N9/45 , H04N9/641 , H04N9/642 , H04N11/143 , H04N11/20 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/59 , H04N19/61 , H04N21/42204 , H04N21/42653 , H04N21/4305 , H04N21/4316 , H04N21/434 , H04N21/440263 , H04N21/4438 , H04N21/47
摘要： A graphics display system integrated circuit is used in a set-top box for controlling a television display. The graphics display system processes analog video input, digital video input, and graphics input. The system incorporates a unified memory architecture that is shared by the graphics system, a CPU, and other peripherals. The unified memory architecture uses real time scheduling to service tasks. Critical instant analysis is used to find a schedule for memory usage that does not affect memory requirements of real time tasks while at the same time servicing non-real-time tasks as needed.
摘要翻译：在用于控制电视显示器的机顶盒中使用图形显示系统集成电路。图形显示系统处理模拟视频输入，数字视频输入和图形输入。该系统包含由图形系统，CPU和其他外围设备共享的统一存储器架构。统一存储器架构使用实时调度来服务任务。关键瞬时分析用于查找不影响实时任务的内存需求的内存使用计划，同时根据需要为非实时任务进行服务。

5. 发明授权

US08711452B2 Processing color and panchromatic pixels 有权
标题翻译：处理颜色和全色像素
公开(公告)号：US08711452B2
公开(公告)日：2014-04-29
申请号：US13618593
申请日：2012-09-14
申请人： John F. Hamilton, Jr. , John T. Compton
发明人： John F. Hamilton, Jr. , John T. Compton
IPC分类号： H04N1/64 , H04N5/235 , H04N5/355 , H04N9/45
CPC分类号： H04N9/045
摘要： A method for forming a final digital color image includes capturing an image using an image sensor having panchromatic pixels and color pixels corresponding to at least two color photoresponses; providing from the captured image a digital panchromatic image and an intermediate digital color image; and using the digital panchromatic image and the intermediate digital color image to provide the final digital color image.
摘要翻译：用于形成最终数字彩色图像的方法包括使用具有全色像素的图像传感器和与至少两个颜色光响应对应的彩色像素捕获图像; 从拍摄图像提供数字全色图像和中间数字彩色图像; 并使用数字全色图像和中间数字彩色图像来提供最终的数字彩色图像。

6. 发明授权

US07545937B2 Chrominance processing arrangement having immunity to colorstripe encoding 有权
标题翻译：色度处理装置具有对色带编码的抗扰性
公开(公告)号：US07545937B2
公开(公告)日：2009-06-09
申请号：US10164683
申请日：2002-06-07
申请人： Mark Francis Rumreich
发明人： Mark Francis Rumreich
IPC分类号： H04N7/167 , H04N9/45 , H04N5/46 , H03L7/00
CPC分类号： H04N9/66 , H04N9/45
摘要： A video system (100) includes a chrominance processing arrangement (200). The chrominance processing arrangement (200) includes a burst accumulator (240) operative to detect a polarity inversion within a burst interval associated with a horizontal line of video information, and generate at least one output signal that compensates for the detected polarity inversion.
摘要翻译：视频系统（100）包括色度处理装置（200）。色度处理装置（200）包括突发累加器（240），用于检测在与视频信息的水平行相关联的突发间隔内的极性反转，并产生补偿检测到的极性反转的至少一个输出信号。

7. 发明授权

US07471338B2 Synchronous image signal data generator 失效
标题翻译：同步图像信号数据发生器
公开(公告)号：US07471338B2
公开(公告)日：2008-12-30
申请号：US11028866
申请日：2005-01-05
申请人： Kotaro Esaki
发明人： Kotaro Esaki
IPC分类号： H04N5/06 , H04N9/45 , H04N9/455
CPC分类号： H04N5/0675
摘要： In order to reduce the circuit scale and the manufacturing cost by decreasing the amount of data to be stored, a synchronizing signal data generating circuit outputs, at each timing, relative synchronizing signal data showing the ratio of a synchronizing signal level to an amplitude level of the synchronizing signal, a multiplier multiplies synchronizing signal amplitude level data, a divider divides by the maximum value N of image signal data which can be outputted from the synchronizing signal data generating circuit, thereby the synchronizing signal data showing actual synchronizing signal level is provided, and an adder adds input image signal data thereto, whereby output image signal data, in which the synchronizing signal data is superposed on the input image signal data, is generated.
摘要翻译：为了通过减少要存储的数据量来减小电路规模和制造成本，同步信号数据生成电路在每个定时输出表示同步信号电平与振幅电平的比率的相对同步信号数据同步信号，乘法器乘以同步信号幅度电平数据，除法器除以可从同步信号数据产生电路输出的图像信号数据的最大值N，从而提供表示实际同步信号电平的同步信号数据，并且加法器将输入图像信号数据加到其上，由此产生其中同步信号数据叠加在输入图像信号数据上的输出图像信号数据。

8. 发明授权

US07391472B1 System and method for adaptive color burst phase correction 有权
标题翻译：自适应色同步相位校正的系统和方法
公开(公告)号：US07391472B1
公开(公告)日：2008-06-24
申请号：US11031124
申请日：2005-01-05
申请人： Neil D. Woodall
发明人： Neil D. Woodall
IPC分类号： H04N9/89 , H04N9/45 , H04L7/00
CPC分类号： H04N9/78
摘要： We describe and claim an adaptive color burst phase correction system and method. The adaptive color burst phase correction system includes a signal detector to extract a color burst from a video signal, the color burst including a phase and an amplitude, an adaptive phase corrector to adjust the color burst phase responsive to corruption in the color burst, a Y/C separator to separate luminance and chrominance data from the video signal, responsive to the adjusted color burst phase, and a panel to display the luminance and chrominance data. The adaptive phase corrector includes a corruption detector to detect corruption in a color burst, a selector to select a phase correction value responsive to the detected corruption, and a phase adjuster to adjust a color burst phase responsive to the phase correction value.
摘要翻译：我们描述并要求自适应色同步相位校正系统和方法。自适应色同步相位校正系统包括信号检测器，用于从视频信号中提取色同步信号，色同步信号包括相位和幅度，自适应相位校正器，以响应于色同步脉冲中的损坏来调整色同步相位; Y / C分离器，用于根据调整的色同步相位分离来自视频信号的亮度和色度数据，以及显示亮度和色度数据的面板。自适应相位校正器包括：检测器，用于检测彩色脉冲串中的损坏;响应于检测到的损坏选择相位校正值的选择器;以及响应于相位校正值调整色同步相位的相位调整器。

9. 发明申请

US20050078218A1 Frame signal phase adjuster 失效
标题翻译：帧信号相位调节器
公开(公告)号：US20050078218A1
公开(公告)日：2005-04-14
申请号：US10943885
申请日：2004-09-20
申请人： Tomomi Hara
发明人： Tomomi Hara
IPC分类号： H04N5/05 , H04N5/12 , H04N9/45
CPC分类号： H04N5/12
摘要： A frame signal phase adjuster comprises units for inputting a parallel clock and a reference signal (22-4 and 22-1); generating a frame signal from the reference signal (22-1), adjusting a phase of the frame signal (22-3), generating an adjusted frame signal synchronized by the parallel clock from the parallel clock and the adjusted frame signal (22-4), generating a frame reset pulse signal based on the parallel clock and the adjusted frame signal synchronized by the parallel clock (22-2), and outputting the frame reset pulse signal (22-2). The unit (22-4) adjusts the phase of the frame signal so that the frame signal is constantly HIGH or LOW throughout a setup time and a hold time.
摘要翻译：帧信号相位调整器包括用于输入并行时钟和参考信号（22-4和22-1）的单元; 从所述参考信号（22-1）产生帧信号，调整所述帧信号（22-3）的相位，产生由所述并行时钟与所述并行时钟同步的经调整帧信号（22-4 ），基于并行时钟产生帧复位脉冲信号，并且通过并行时钟（22-2）同步的被调整帧信号，并输出帧复位脉冲信号（22-2）。单元（22-4）调整帧信号的相位，使得帧信号在整个建立时间和保持时间内始终为高或低。

10. 发明申请

US20050024369A1 Video and graphics system with a single-port RAM 失效
标题翻译：具有单端口RAM的视频和图形系统
公开(公告)号：US20050024369A1
公开(公告)日：2005-02-03
申请号：US10901648
申请日：2004-07-29
申请人： Xiaodong Xie
发明人： Xiaodong Xie
IPC分类号： G06T9/00 , G09G1/16 , G09G5/00 , G09G5/02 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/34 , G09G5/36 , G09G5/39 , G09G5/395 , G09G5/397 , G09G5/42 , H04N5/14 , H04N5/44 , H04N5/445 , H04N5/45 , H04N5/46 , H04N7/01 , H04N9/45 , H04N9/64 , H04N11/14 , H04N11/20 , G06F12/00 , G06F13/18 , G06F15/167
CPC分类号： G09G5/001 , G06T9/007 , G09G5/02 , G09G5/024 , G09G5/026 , G09G5/06 , G09G5/12 , G09G5/14 , G09G5/28 , G09G5/346 , G09G5/36 , G09G2310/0224 , G09G2320/0247 , G09G2340/02 , G09G2340/0407 , G09G2340/10 , G09G2340/125 , G09G2360/02 , G09G2360/121 , G09G2360/125 , G09G2360/128 , H04N5/14 , H04N5/4401 , H04N5/44504 , H04N5/44508 , H04N5/45 , H04N5/46 , H04N7/0135 , H04N9/45 , H04N9/641 , H04N11/143 , H04N11/20 , H04N21/42653 , H04N21/42692 , H04N21/4305 , H04N21/4307 , H04N21/4316 , H04N21/440218 , H04N21/8146
摘要： A video and graphics system has an input for receiving compressed video data and an input for receiving graphics data. The compressed video data may include HDTV video and/or SDTV video, and may be included in compressed data streams such as an MPEG-2 Transport stream. The video and graphics system also includes a video decoder for processing the compressed video data to generate a video for displaying, a display engine for processing the graphics data to generate graphics for displaying, and an overlaying system for compositing the video and the graphics to generate an output video. The display engine includes a memory used during conversion of a graphics format from a first format to a second format to be in a format compatible with a video format The memory may be implemented in a single-port SRAM configured to simulate a dual-port SRAM. The system may be integrated on an integrated circuit chip.
摘要翻译：视频和图形系统具有用于接收压缩视频数据的输入和用于接收图形数据的输入。压缩视频数据可以包括HDTV视频和/或SDTV视频，并且可以包括在诸如MPEG-2传输流的压缩数据流中。视频和图形系统还包括用于处理压缩视频数据以生成用于显示的视频的视频解码器，用于处理图形数据以生成用于显示的图形的显示引擎，以及用于合成视频和图形的叠加系统以产生输出视频。显示引擎包括将图形格式从第一格式转换成第二格式的存储器，以与格式兼容的格式。存储器可以在被配置为模拟双端口SRAM的单端口SRAM中实现。该系统可以集成在集成电路芯片上。

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