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1. 发明授权

US11903331B2 Digital circuits comprising quantum wire resonant tunneling transistors 有权
公开(公告)号：US11903331B2
公开(公告)日：2024-02-13
申请号：US17467188
申请日：2021-09-04
申请人： Koucheng Wu
发明人： Koucheng Wu
IPC分类号： H10N60/10 , H10N60/01 , H10N69/00 , H03K19/20 , H03K19/088 , H03K19/00 , H03K19/082 , H03K17/60 , H01L29/04 , H01L29/66 , H01L29/76 , H01L29/15 , H01L29/775 , H03K17/92 , H03K19/195
CPC分类号： H10N60/128 , H01L29/045 , H01L29/151 , H01L29/66439 , H01L29/66931 , H01L29/7606 , H01L29/775 , H03K17/60 , H03K17/92 , H03K19/001 , H03K19/082 , H03K19/088 , H03K19/195 , H03K19/20 , H10N60/0884 , H10N69/00
摘要： A digital circuit includes at least one quantum wire resonant tunneling transistor that includes an emitter terminal, a base terminal, a collector terminal, an emitter region in connection with the emitter terminal, a base region in connection with the base terminal, a collector region in connection with the collector terminal, an emitter barrier region between the emitter region and the base region, and a collector barrier region between the collector region and the base region. At least one of the emitter region, the base region, and the collector region includes a plurality of metal quantum wires.

2. 发明授权

US11489526B2 Current steering level-shifter 有权
公开(公告)号：US11489526B2
公开(公告)日：2022-11-01
申请号：US16882407
申请日：2020-05-22
申请人： Intel Corporation
发明人： Andres Malavasi Mora , Jaydeep Kulkarni , Anupama Thaploo , Muhammad Khellah
IPC分类号： H03K19/082 , H03K19/0175 , H03K19/0948
摘要： Described is a level-shifter that can save area between voltage domains with limited voltage differential, and further save power by steering current between two power supply rails. The level-shifter comprises: an input to receive a first signal between a first reference rail and a second reference rail; an output to provide a second signal the first reference rail and a third reference rail, wherein in a voltage level of the third reference rail is higher than a voltage level of the second reference rail, and wherein a voltage level of the first reference is lower than the voltage level of the second reference rail and the third reference rail; and a circuitry coupled to the input and the output, wherein the circuitry is to steer current from the third reference rail to the second reference rail.

3. 发明授权

US10848157B2 Level converter and a method for converting level values in vehicle control devices 有权
公开(公告)号：US10848157B2
公开(公告)日：2020-11-24
申请号：US16629286
申请日：2018-06-12
申请人： KNORR-BREMSE SYSTEME FUER NUTZFAHRZEUGE GMBH
发明人： Thomas Feucht
IPC分类号： H03K19/082 , H03K19/0175 , H03K19/0185 , H03K19/094 , H03K5/003
CPC分类号： H03K19/0826 , H03K19/017509 , H03K19/018521 , H03K19/09429 , H03K5/003
摘要： A level converter for a vehicle control device, including: a first voltage terminal; a second voltage terminal; at least one output terminal; an input terminal; a first switch for switching a first current path between the first voltage terminal and the at least one output terminal or one of the output terminals; and a second switch for switching a second current path between the second voltage terminal and the at least one output terminal or another of the output terminals; the first and second switches being switchable in response to different levels at the input terminal so that when a first level is present at the input terminal, the first switch is closed and the second switch is open, and so that when a second level is present, the first switch is open and the second switch is closed. Also described is a related control device, utility vehicle and method.

4. 发明授权

US09209808B2 Asymmetrical bus keeper 有权
标题翻译：不对称巴士管理员
公开(公告)号：US09209808B2
公开(公告)日：2015-12-08
申请号：US13927519
申请日：2013-06-26
申请人： BLACKBERRY LIMITED
发明人： John Douglas McGinn
IPC分类号： H03K17/16 , H03K19/0185 , H03K19/082 , H03K19/018 , H03K19/094 , H03K19/0175
CPC分类号： H03K19/018507 , H03K19/017509 , H03K19/01806 , H03K19/082 , H03K19/09403
摘要： Various embodiments are described herein for an asymmetrical bus keeper circuit that provides asymmetrical drive towards one logic level. The asymmetrical bus keeper circuit comprises a first inverter stage having an input node and an output node, an asymmetrical inverter stage having an input node and an output node and a feedback stage with an input node and an output node. The input node of the asymmetrical inverter stage is connected to the output node of the first inverter stage. The input node of the feedback stage connected to the output node of the asymmetrical inverter stage and the output node of the feedback stage connected to the input node of the first inverter stage. The asymmetrical stage provides asymmetrical drive towards one logic level.
摘要翻译：这里描述了用于向一个逻辑电平提供不对称驱动的非对称总线保持器电路的各种实施例。非对称总线保持器电路包括具有输入节点和输出节点的第一反相器级，具有输入节点和输出节点的非对称逆变器级和具有输入节点和输出节点的反馈级。不对称反相器级的输入节点连接到第一反相器级的输出节点。反馈级的输入节点连接到非对称逆变器级的输出节点，反馈级的输出节点连接到第一级逆变器级的输入节点。非对称阶段向一个逻辑水平提供不对称驱动。

5. 发明授权

US08198918B1 Capacitor cell supporting circuit operation at higher-voltages while employing capacitors designed for lower voltages 有权
标题翻译：电容器电池支持电路在较高电压下工作，同时使用为较低电压设计的电容器
公开(公告)号：US08198918B1
公开(公告)日：2012-06-12
申请号：US12979387
申请日：2010-12-28
申请人： Karthik Rajagopal
发明人： Karthik Rajagopal
IPC分类号： H03K19/094 , H03K19/082
CPC分类号： H03K19/018521 , H03K19/094
摘要： An integrated circuit (IC) includes a functional circuit and a capacitor cell. The functional circuit may operate with one of two power supply voltages. The capacitor cell is used to provide power supply decoupling for the functional circuit, and includes multiple capacitors, each designed to withstand a maximum voltage equal to the lower of the two power supply voltages. When the functional circuit is to operate with the higher of the two power supply voltages, the capacitors in the capacitor cell are coupled in a series arrangement between power supply and ground terminals of the IC. When the functional circuit is to operate with the lower of the two power supply voltages, the capacitors in the capacitor cell are coupled in a parallel arrangement between the power supply and ground terminals. In an embodiment, the functional circuit is an input-output (I/O) circuit powered by 1.8V or 3.3V power supplies.
摘要翻译：集成电路（IC）包括功能电路和电容器单元。功能电路可以用两个电源电压中的一个来工作。电容器电池用于为功能电路提供电源去耦，并且包括多个电容器，每个电容器被设计成承受等于两个电源电压中较低者的最大电压。当功能电路以两个电源电压中的较高者工作时，电容器单元中的电容器以IC的电源和接地端子之间的串联布置耦合。当功能电路以两个电源电压中的较低者工作时，电容器单元中的电容器以并联的方式耦合在电源和接地端子之间。在一个实施例中，功能电路是由1.8V或3.3V电源供电的输入输出（I / O）电路。

6. 发明授权

US08159270B2 Circuitry and methods minimizing output switching noise through split-level signaling and bus division enabled by a third power supply 有权
标题翻译：电路和方法通过由第三电源使能的分级信号和总线划分来最小化输出开关噪声
公开(公告)号：US08159270B2
公开(公告)日：2012-04-17
申请号：US12259625
申请日：2008-10-28
申请人： Timothy M. Hollis
发明人： Timothy M. Hollis
IPC分类号： H03K19/082
CPC分类号： G11C7/02 , G11C7/1051 , G11C7/1057 , G11C11/4074 , H03K19/00353
摘要： Disclosed herein are circuitry and methods for transmitting data across a parallel bus using both high common mode and low common mode signaling. The transmitter stages are configured to work with two of three possible power supply voltages: a high Vddq voltage, a low Vssq voltage, and an intermediate Vx voltage. In one embodiment, the odd numbered transmitter stages, that drive the odd numbered outputs to the bus, use the Vddq and Vx supplies, such that the odd numbered outputs comprise high common mode signals. The even numbered transmitter stages, that drive the even numbered outputs to the bus, use the Vx and Vssq supplies, such that the even numbered outputs comprise low common mode signals. With the transmitter and power supplies so configured, no one of the three power supplies must source or sink current to or from more than half of the transmitters at any given time, which reduces power supply loading and minimizes switching noise. As a result, use of the technique may dispense with the need to provide power supply isolation at the transmitters.
摘要翻译：这里公开了用于使用高共模和低共模信令在并行总线上传输数据的电路和方法。发射器级配置为工作在三种可能的电源电压中的两种：高Vddq电压，低Vssq电压和中间Vx电压。在一个实施例中，将奇数编号的输出驱动到总线的奇数发送器级使用Vddq和Vx电源，使得奇数输出包括高共模信号。将偶数编号的输出驱动到总线的偶数发送器级使用Vx和Vssq电源，使得偶数输出包括低共模信号。在发射器和电源如此配置的情况下，在任何给定时间，三个电源中的任何一个电源都不得向或超过一半以上的发射器供电或吸收电流，从而减少电源负载并最大限度地减少开关噪声。因此，使用该技术可以省去在发射机处提供电源隔离的需要。

7. 发明授权

US07880502B2 Logic circuit 有权
标题翻译：逻辑电路
公开(公告)号：US07880502B2
公开(公告)日：2011-02-01
申请号：US12677069
申请日：2008-08-25
申请人： Haruo Kawakami , Yasushi Ogimoto
发明人： Haruo Kawakami , Yasushi Ogimoto
IPC分类号： H03K19/082
CPC分类号： G11C11/16 , H03K3/313
摘要： A logic circuit with a simple configuration and good current efficiency is provided. The logic circuit includes a two-terminal bistable switching element (1) having characteristics which maintain states, a first switching element (25) one end of which is connected to one terminal of the two-terminal bistable switching element (1), a second switching element (29) one end of which is connected to the other terminal of the two-terminal bistable switching element (1) via a resistance element (27), and first and second pulse input terminals (33, 37) respectively connected to the one terminal and the other terminal of the two-terminal bistable switching element (1). A bias voltage is applied across the other end of the first switching element (25) and the other end of the second switching element (27), and a trigger pulse is input from the first and second pulse input terminals (33, 37).
摘要翻译：提供了具有简单配置和良好电流效率的逻辑电路。逻辑电路包括具有维持状态特性的双端双稳态开关元件（1），其一端连接到两端双稳态开关元件（1）的一个端子的第一开关元件（25），第二开关元件开关元件（29），其一端经由电阻元件（27）与两端双稳态开关元件（1）的另一端子连接，第一和第二脉冲输入端子（33,37）分别与两端子双稳态开关元件（1）的一个端子和另一个端子。跨越第一开关元件（25）的另一端和第二开关元件（27）的另一端施加偏置电压，并且从第一和第二脉冲输入端子（33,37）输入触发脉冲。

8. 发明授权

US07823003B1 Voltage referencing clock for source-synchronous multi-level signal buses 有权
标题翻译：源同步多电平信号总线的电压参考时钟
公开(公告)号：US07823003B1
公开(公告)日：2010-10-26
申请号：US11626265
申请日：2007-01-23
申请人： Christopher Cheng
发明人： Christopher Cheng
IPC分类号： G06F1/04 , H03K19/082
CPC分类号： H03K19/0002
摘要： An input circuit is provided for coupling to a source-synchronous multi-level bus carrying data, clock, and complementary clock signals. The clock and complementary clock signals have a less than full voltage swing than the data signal so they can act as reference voltages for the data signal. The circuit includes a first differential receiver having inputs coupled to the data and the clock signals, a second differential receiver having inputs coupled to the data signal and a reference signal, and a third differential receiver having inputs coupled to the data and the complementary clock signals. The circuit further includes first, second, and third flip-flops having data inputs coupled to outputs of the first, the second, and the third differential receivers, and clock inputs coupled to a delayed clock signal generated from the clock and the complementary clock signals. The outputs of the flip-flops determine the level of the data signal.
摘要翻译：提供输入电路用于耦合到承载数据，时钟和互补时钟信号的源同步多电平总线。时钟和互补时钟信号具有比数据信号小的全电压摆幅，因此它们可以作为数据信号的参考电压。电路包括具有耦合到数据和时钟信号的输入的第一差分接收器，具有耦合到数据信号和参考信号的输入的第二差分接收器，以及具有耦合到数据和互补时钟信号的输入的第三差分接收器。电路还包括具有耦合到第一，第二和第三差分接收器的输出的数据输入的第一，第二和第三触发器，以及耦合到从时钟和互补时钟信号产生的延迟时钟信号的时钟输入。触发器的输出确定数据信号的电平。

9. 发明授权

US07795922B2 Decoder circuit 有权
标题翻译：解码电路
公开(公告)号：US07795922B2
公开(公告)日：2010-09-14
申请号：US12361755
申请日：2009-01-29
申请人： Mitsuhiro Tomoeda , Makoto Muneyasu , Masahiro Hosoda
发明人： Mitsuhiro Tomoeda , Makoto Muneyasu , Masahiro Hosoda
IPC分类号： G11C8/00 , H03K19/082 , H03K19/094
CPC分类号： H03K19/20 , G11C8/08 , G11C8/10 , G11C16/08
摘要： A normally operable decoder circuit is obtained without entailing a delay in decoding operation, an increase in circuit area, and an increase in circuit design cost. An NMOS transistor in a high-voltage circuit portion is inserted between the output of a NAND gate and a node, and receives an input signal at the gate electrode thereof. A load current generating portion in the high-voltage circuit portion includes PMOS transistors coupled in series between a high power supply voltage and the node. One of the PMOS transistor receives a control signal at the gate electrode thereof. The other PMOS transistor receives a control signal at the gate electrode thereof. An inverter receives a signal obtained from the node as an input signal, and outputs the inverted signal thereof as an output signal.
摘要翻译：获得正常可操作的解码器电路，而不需要解码操作的延迟，电路面积的增加和电路设计成本的增加。高电压电路部分中的NMOS晶体管插在NAND门与节点的输出端之间，并在其栅电极处接收输入信号。高压电路部分中的负载电流产生部分包括串联耦合在高电源电压和节点之间的PMOS晶体管。一个PMOS晶体管在其栅电极处接收控制信号。另一个PMOS晶体管在其栅电极处接收控制信号。逆变器接收从节点获得的信号作为输入信号，并将其反相信号作为输出信号输出。

10. 发明申请

US20100165708A1 MEMORY CONTROLLER AND DECODER 有权
标题翻译：内存控制器和解码器
公开(公告)号：US20100165708A1
公开(公告)日：2010-07-01
申请号：US12397614
申请日：2009-03-04
申请人： Cheng-Sheng Lee
发明人： Cheng-Sheng Lee
IPC分类号： G11C11/00 , H03K19/082
CPC分类号： H03K19/0013 , G11C8/08 , G11C8/10
摘要： A memory controller and a decoder are provided. The decoder is adapted to the memory controller. The decoder includes a first transistor to a fourth transistor. Gates of the first to the fourth transistor are coupled to a first to a fourth control signal respectively. A first terminal and a second terminal of the first transistor are coupled to a first voltage and a first terminal of the second transistor respectively. First terminals and second terminals of the third transistor and the fourth transistor are coupled to a second terminal of the second transistor and a second voltage respectively. When the first transistor and the second transistor are turned off, a voltage of the second control signal is lower than a voltage of the first control signal. Thereby, a gate-induced drain leakage (GIDL) current of the transistors is reduced.
摘要翻译：提供存储器控制器和解码器。解码器适用于存储器控制器。解码器包括到第四晶体管的第一晶体管。第一至第四晶体管的栅极分别耦合到第一至第四控制信号。第一晶体管的第一端子和第二端子分别耦合到第一电压和第二晶体管的第一端子。第三晶体管和第四晶体管的第一端子和第二端子分别耦合到第二晶体管的第二端子和第二电压。当第一晶体管和第二晶体管截止时，第二控制信号的电压低于第一控制信号的电压。因此，晶体管的栅极引起的漏极漏极（GIDL）电流减小。

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