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1. 发明申请

US20100019797A1 Mix Mode Driver For Traces Of Different Lengths 有权
标题翻译：混合模式驱动程序用于不同长度的轨迹
公开(公告)号：US20100019797A1
公开(公告)日：2010-01-28
申请号：US12571740
申请日：2009-10-01
申请人： Christopher Cheng , David Chu
发明人： Christopher Cheng , David Chu
IPC分类号： H03K19/173 , G06F7/50 , H03K19/0175 , G06G7/14
CPC分类号： H03K19/00369 , H03K19/00323
摘要： A method for a mix mode driver to accommodate traces of different lengths includes storing in the mix mode driver a set of one or more control signals and coefficient signals for a trace length. The one or more control signals select a number of the stages to generate a variable amplitude data output signal. Each stage is operable to increase or decrease a data signal, and each of the coefficient signals determines the magnitude of increase or decrease of the data input signal by a stage. A method for operating the mix mode driver includes generating the variable amplitude data output signal with one or more of the stages, and providing the variable amplitude data output signal to a trace.
摘要翻译：用于混合模式驱动器以适应不同长度的轨迹的方法包括在混合模式驱动器中存储用于跟踪长度的一组一个或多个控制信号和系数信号。一个或多个控制信号选择多个级以产生可变幅度数据输出信号。每个级可操作以增加或减少数据信号，并且系数信号中的每一个确定数据输入信号通过级的增加或减小的幅度。用于操作混合模式驱动器的方法包括利用一个或多个级产生可变幅度数据输出信号，并将可变幅度数据输出信号提供给跟踪。

2. 发明申请

US20060176308A1 Multidimensional datapath processing in a video processor 有权
公开(公告)号：US20060176308A1
公开(公告)日：2006-08-10
申请号：US11267638
申请日：2005-11-04
申请人： Ashish Karandikar , Shirish Gadre , Stephen Lew , Christopher Cheng
发明人： Ashish Karandikar , Shirish Gadre , Stephen Lew , Christopher Cheng
IPC分类号： G06T1/00
CPC分类号： G06T1/60 , G06F3/14 , G06F9/3851 , G06F9/3887 , G06F12/0877 , G06T1/20 , G09G5/37 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/61 , H04N19/82 , H04N19/85 , H04N19/86
摘要： A multidimensional datapath processing system for a video processor for executing video processing operations. The video processor includes a scalar execution unit configured to execute scalar video processing operations and a vector execution unit configured to execute vector video processing operations. A data store memory is included for storing data for the vector execution unit. The data store memory includes a plurality of tiles having symmetrical bank data structures arranged in an array. The bank data structures are configured to support accesses to different tiles of each bank.

3. 发明授权

US07802153B1 Trainable link 有权
标题翻译：可训练的链接
公开(公告)号：US07802153B1
公开(公告)日：2010-09-21
申请号：US11608241
申请日：2006-12-07
申请人： Michel P. Cekleov , Christopher Cheng , Greg L. Dykema , David Chu
发明人： Michel P. Cekleov , Christopher Cheng , Greg L. Dykema , David Chu
IPC分类号： G01R31/28 , H04L7/00 , H04B17/00 , G06F11/00
CPC分类号： H04L7/10 , H04L7/0008 , H04L7/0037 , H04L7/043
摘要： A method is provided to align clock and data signals over a source-synchronous link. The method includes sending header data and a default clock signal over the link. The header indicates a start of a training packet and the default clock signal ensures that the header is received without error. The method further includes providing a long clock pulse, phase shifting the clock signal during the long clock pulse, and thereafter sending training data and the clock signal over the link. The above steps are repeated until the training data are received with error. At that point, the phase shift of the clock signal is saved as a boundary of an optimal alignment. The above steps are then repeated with the clock signal shifted in a different direction. Once another boundary is located, the boundary midpoint is saved as the phase shift that provides the optimal alignment.
摘要翻译：提供了一种通过源同步链路对准时钟和数据信号的方法。该方法包括通过链路发送报头数据和默认时钟信号。标题指示训练分组的开始，并且默认时钟信号确保接收到报头而没有错误。该方法还包括提供长时钟脉冲，在长时钟脉冲期间相移时钟信号，然后通过链路发送训练数据和时钟信号。重复上述步骤，直到接收到训练数据为止。此时，时钟信号的相移被保存为最佳对齐的边界。然后以不同方向移位的时钟信号重复上述步骤。一旦找到另一个边界，边界中点就被保存为提供最佳对齐的相移。

4. 发明授权

US07622945B1 Mix mode driver for traces of different lengths 有权
标题翻译：混合模式驱动器，用于不同长度的痕迹
公开(公告)号：US07622945B1
公开(公告)日：2009-11-24
申请号：US11614031
申请日：2006-12-20
申请人： Christopher Cheng , David Chu
发明人： Christopher Cheng , David Chu
IPC分类号： H03K19/003
CPC分类号： H03K19/00369 , H03K19/00323
摘要： A method for a mix mode driver to accommodate traces of different lengths includes sequentially shifting values of a data signal to a number of stages and sequentially amplifying the values of the data signal at least one stage. Depending on the length of trace for the data signal, the method further includes providing at least one amplifying coefficient to at least one stage and coupling a subset of the stages to an adder. The method finally includes outputting the data signal from the adder to the trace.
摘要翻译：用于混合模式驱动器以适应不同长度的迹线的方法包括将数据信号的值顺序地移位到多个级，并且在至少一个级中顺序地放大数据信号的值。取决于数据信号的迹线的长度，该方法还包括向至少一个级提供至少一个放大系数，并将该级的子集耦合到加法器。该方法最后包括将数据信号从加法器输出到轨迹。

5. 发明申请

US20070208901A1 LAYERED CROSSBAR FOR INTERCONNECTION OF MULTIPLE PROCESSORS AND SHARED MEMORIES 有权
标题翻译：用于互连多个处理器和共享存储器的层叠交叉
公开(公告)号：US20070208901A1
公开(公告)日：2007-09-06
申请号：US11463842
申请日：2006-08-10
申请人： Stephen Purcell , Christopher Cheng
发明人： Stephen Purcell , Christopher Cheng
IPC分类号： G06F13/00
CPC分类号： G06F13/1657 , G06F13/4022 , G06F15/17375
摘要： A method and apparatus includes a plurality of processor groups each having a plurality of processor switch chips each having a plurality of processors and a processor crossbar, each processor connected to the processor crossbar; a plurality of switch groups each having a plurality of switch crossbar chips each having a plurality of switch groups each having a plurality of switch crossbar chips each having a plurality of switch crossbars each connected to a processor crossbar in each processor group, wherein no two switch crossbars in a switch group are connected to the same processor crossbar; a plurality of memory groups having a plurality of memory switch chips each having a plurality of memory controllers and a memory crossbar, each memory controller connected to the memory crossbar, each memory crossbar in each memory group connected to all of the switch crossbar in a corresponding one of the switch groups, wherein no two memory groups are connected to the same switch group.
摘要翻译：一种方法和装置包括多个处理器组，每个处理器组具有多个处理器开关芯片，每个处理器开关芯片具有多个处理器和处理器交叉开关，每个处理器连接到处理器交叉开关; 多个开关组，每个具有多个开关交叉开关组，每个开关交叉开关组具有多个开关组，每个开关组具有多个开关交叉开关组，每个开关交叉开关组具有多个开关交叉开关，每个开关交叉连接到每个处理器组中的处理器交叉开关，其中没有两个开关交换机组中的交叉开关连接到相同的处理器交叉开关; 具有多个存储器开关芯片的多个存储器组，每个存储器开关芯片各自具有多个存储器控制器和存储器交叉开关，每个存储器控制器连接到存储器交叉开关，每个存储器组中的每个存储器交叉开关连接到相应的所有开关交叉开关其中一个交换机组，其中没有两个存储器组连接到相同的交换机组。

6. 发明授权

US07911222B2 Mix mode driver for traces of different lengths 有权
标题翻译：混合模式驱动器，用于不同长度的痕迹
公开(公告)号：US07911222B2
公开(公告)日：2011-03-22
申请号：US12571740
申请日：2009-10-01
申请人： Christopher Cheng , David Chu
发明人： Christopher Cheng , David Chu
IPC分类号： H03K19/003
CPC分类号： H03K19/00369 , H03K19/00323
摘要： A method for a mix mode driver to accommodate traces of different lengths includes storing in the mix mode driver a set of one or more control signals and coefficient signals for a trace length. The one or more control signals select a number of the stages to generate a variable amplitude data output signal. Each stage is operable to increase or decrease a data signal, and each of the coefficient signals determines the magnitude of increase or decrease of the data input signal by a stage. A method for operating the mix mode driver includes generating the variable amplitude data output signal with one or more of the stages, and providing the variable amplitude data output signal to a trace.
摘要翻译：用于混合模式驱动器以适应不同长度的轨迹的方法包括在混合模式驱动器中存储用于跟踪长度的一组一个或多个控制信号和系数信号。一个或多个控制信号选择多个级以产生可变幅度数据输出信号。每个级可操作以增加或减少数据信号，并且系数信号中的每一个确定数据输入信号通过级的增加或减小的幅度。用于操作混合模式驱动器的方法包括利用一个或多个级产生可变幅度数据输出信号，并将可变幅度数据输出信号提供给跟踪。

7. 发明申请

US20060176309A1 Video processor having scalar and vector components 有权
标题翻译：具有标量和矢量分量的视频处理器
公开(公告)号：US20060176309A1
公开(公告)日：2006-08-10
申请号：US11267700
申请日：2005-11-04
申请人： Shirish Gadre , Ashish Karandikar , Stephen Lew , Christopher Cheng
发明人： Shirish Gadre , Ashish Karandikar , Stephen Lew , Christopher Cheng
IPC分类号： G06T1/00
CPC分类号： G06T1/60 , G06F3/14 , G06F9/3851 , G06F9/3887 , G06F12/0877 , G06T1/20 , G09G5/37 , H04N19/42 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/61 , H04N19/82 , H04N19/85 , H04N19/86
摘要： A video processor for executing video processing operations. The video processor includes a host interface for implementing communication between the video processor and a host CPU. A memory interface is included for implementing communication between the video processor and a frame buffer memory. A scalar execution unit is coupled to the host interface and the memory interface and is configured to execute scalar video processing operations. A vector execution unit is coupled to the host interface and the memory interface and is configured to execute vector video processing operations.
摘要翻译：一种用于执行视频处理操作的视频处理器。视频处理器包括用于实现视频处理器和主机CPU之间的通信的主机接口。包括用于实现视频处理器和帧缓冲存储器之间的通信的存储器接口。标量执行单元耦合到主机接口和存储器接口，并且被配置为执行标量视频处理操作。向量执行单元耦合到主机接口和存储器接口，并被配置为执行向量视频处理操作。

8. 发明授权

US06310489B1 Method to reduce wire-or glitch in high performance bus design to improve bus performance 失效
标题翻译：在高性能总线设计中减少线或毛刺的方法，以提高总线性能
公开(公告)号：US06310489B1
公开(公告)日：2001-10-30
申请号：US08640096
申请日：1996-04-30
申请人： Leo Yuan , Christopher Cheng
发明人： Leo Yuan , Christopher Cheng
IPC分类号： H03K1716
CPC分类号： H04L25/028 , H04L25/0278 , H04L25/0292 , H04L25/0298
摘要： A system and method of reducing wire-or glitch to improve bus speeds. In a system that supports wire-or functions, the rise time of the wave created by the off-going driver is controlled. The off-going wave is forced to climb gradually such that one propagation delay of the loaded bus later, it is only marginally above a high threshold voltage. The fall time of the wave created by an on-going driver is minimized such that a strong negative going voltage propagates down the bus. This strong negative going voltage drags a composite wave on the bus (i.e. the combination of the waves of the on-going driver and the off-going driver) back below a low threshold voltage approximately one propagation delay after the switching occurs.
摘要翻译：减少线或毛刺以提高总线速度的系统和方法。在支持线或功能的系统中，控制由脱离驱动器创建的波的上升时间。随后的波浪被迫逐渐爬升，使得负载总线的一个传播延迟稍后，仅略高于高阈值电压。由正在进行的驱动器产生的波形的下降时间被最小化，使得强的负向电压沿着总线传播。这个强的负向导通电压将总线上的复合波（即正在进行的驱动器的波的组合和离开的驱动器）拖回低于低阈值电压，在切换发生之后大约一个传播延迟。

9. 发明授权

US6154845A Power failure safe computer architecture 有权
标题翻译：电源故障安全计算机架构
公开(公告)号：US6154845A
公开(公告)日：2000-11-28
申请号：US151484
申请日：1998-09-11
申请人： Alper Ilkbahar , Christopher Cheng
发明人： Alper Ilkbahar , Christopher Cheng
IPC分类号： G06F1/26 , G06F1/30 , G06F11/00
CPC分类号： G06F11/0754 , G06F1/26 , G06F1/30 , G06F11/0724 , G06F11/00 , G06F11/004
摘要： A component powered by a first power supply activates a driving signal. The driving signal indicates that both a second power supply voltage has a magnitude greater than a reference voltage and an enable signal is active. A driver transfers the output signal when the driving signal is active. In a multi-processor computer system implementation, each of two processor cores are independently supplied power by each of two core power supplies while a single I/O power supply supplies power to the I/O rings of both processors. Each processor includes a bus isolation circuit to prevent its respective processor from loading the system bus in the event that a core power supply fails.
摘要翻译：由第一电源供电的部件激活驱动信号。驱动信号指示第二电源电压都具有大于参考电压的幅度，并且使能信号有效。当驱动信号有效时，驱动器传输输出信号。在多处理器计算机系统实现中，两个处理器核心中的每一个由两个核心电源中的每一个独立供电，而单个I / O电源为两个处理器的I / O环供电。每个处理器包括总线隔离电路，以防止其核心电源故障的情况下其各自的处理器加载系统总线。

10. 发明授权

US07823003B1 Voltage referencing clock for source-synchronous multi-level signal buses 有权
标题翻译：源同步多电平信号总线的电压参考时钟
公开(公告)号：US07823003B1
公开(公告)日：2010-10-26
申请号：US11626265
申请日：2007-01-23
申请人： Christopher Cheng
发明人： Christopher Cheng
IPC分类号： G06F1/04 , H03K19/082
CPC分类号： H03K19/0002
摘要： An input circuit is provided for coupling to a source-synchronous multi-level bus carrying data, clock, and complementary clock signals. The clock and complementary clock signals have a less than full voltage swing than the data signal so they can act as reference voltages for the data signal. The circuit includes a first differential receiver having inputs coupled to the data and the clock signals, a second differential receiver having inputs coupled to the data signal and a reference signal, and a third differential receiver having inputs coupled to the data and the complementary clock signals. The circuit further includes first, second, and third flip-flops having data inputs coupled to outputs of the first, the second, and the third differential receivers, and clock inputs coupled to a delayed clock signal generated from the clock and the complementary clock signals. The outputs of the flip-flops determine the level of the data signal.
摘要翻译：提供输入电路用于耦合到承载数据，时钟和互补时钟信号的源同步多电平总线。时钟和互补时钟信号具有比数据信号小的全电压摆幅，因此它们可以作为数据信号的参考电压。电路包括具有耦合到数据和时钟信号的输入的第一差分接收器，具有耦合到数据信号和参考信号的输入的第二差分接收器，以及具有耦合到数据和互补时钟信号的输入的第三差分接收器。电路还包括具有耦合到第一，第二和第三差分接收器的输出的数据输入的第一，第二和第三触发器，以及耦合到从时钟和互补时钟信号产生的延迟时钟信号的时钟输入。触发器的输出确定数据信号的电平。

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