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1. 发明授权

US12112800B2 High speed multi-level cell (MLC) programming in non-volatile memory structures 有权
公开(公告)号：US12112800B2
公开(公告)日：2024-10-08
申请号：US17825048
申请日：2022-05-26
申请人： SanDisk Technologies LLC
发明人： Xiang Yang , Deepanshu Dutta , Muhammad Masuduzzaman , Jiacen Guo
IPC分类号： G11C11/04 , G11C11/56 , G11C16/04 , G11C16/08 , G11C16/10 , G11C16/24 , G11C16/26
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/24 , G11C16/26
摘要： A method for programming a memory array of a non-volatile memory structure, wherein the memory array comprises a population of MLC NAND-type memory cells, and the method comprises: (1) in a first program pulse, programming selected memory cells according to a first programmable state and a second programmable state, and (2) in a second program pulse, programming the selected memory cells according to a third programmable state.

2. 发明授权

US11410071B2 Fermionic simulation gates 有权
公开(公告)号：US11410071B2
公开(公告)日：2022-08-09
申请号：US16753070
申请日：2017-10-02
申请人： Google LLC
发明人： Ryan Babbush
IPC分类号： G11C11/04 , G06N10/00 , H01L29/66
摘要： Methods, systems, and apparatus for simulating a physical system. A Hamiltonian describing the physical system is transformed into a qubit Hamiltonian describing a corresponding system of qubits, the qubit Hamiltonian comprising a transformed kinetic energy operator. The evolution of the system of qubits under the qubit Hamiltonian is simulated, including simulating the evolution of the system of qubits under the transformed kinetic energy operator by applying a fermionic swap network to the system of qubits. The simulated evolution of the system of qubits under the qubit Hamiltonian is used to determine properties of the physical system.

3. 发明授权

US09666245B2 Device having multiple channels with calibration circuit shared by multiple channels 有权
公开(公告)号：US09666245B2
公开(公告)日：2017-05-30
申请号：US14695837
申请日：2015-04-24
申请人： Micron Technology, Inc.
发明人： Tetsuya Arai , Junki Taniguchi
IPC分类号： H03K19/0185 , G11C11/04 , G11C7/04 , G11C11/4093 , G11C5/02 , G11C29/02 , G11C11/401
CPC分类号： G11C7/04 , G11C5/025 , G11C11/401 , G11C11/4093 , G11C29/021 , G11C29/025 , G11C29/028 , G11C2207/105 , G11C2207/2254 , H03K19/018507 , H03K19/018585
摘要： An apparatus includes a first channel, a second channel and a calibration circuit. The first channel includes a first command control circuit. The second channel includes a second command control circuit independent of the first command control circuit. The calibration circuit is shared by the first channel and the second channel to generate a calibration code responsive to a calibration command generated responsive to a first calibration command from the first command control circuit and a second calibration command from the second command control circuit.

4. 发明授权

US09412463B1 Reducing hot electron injection type of read disturb in 3D non-volatile memory for edge word lines 有权
标题翻译：减少用于边缘字线的3D非易失性存储器中的热电子注入类型的读取干扰
公开(公告)号：US09412463B1
公开(公告)日：2016-08-09
申请号：US14728634
申请日：2015-06-02
申请人： SanDisk Technologies Inc.
发明人： Hong-Yan Chen , Yingda Dong
IPC分类号： G11C16/04 , G11C16/34 , G11C16/26 , G11C11/04
CPC分类号： G11C16/3427 , G11C11/04 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C16/26 , G11C16/32 , G11C16/3459
摘要： Read disturb due to hot electron injection is reduced in a 3D memory device by controlling the magnitude and timing of word line and select gate ramp down voltages at the end of a sensing operation. In an example read operation, a predefined subset of word lines includes source-side and drain-side word lines. For the predefined subset of word lines, word line voltages are ramped down before the voltages of the select gates are ramped down. Subsequently, for a remaining subset of word lines, word line voltages are ramped down, but no later than the ramping down of the voltages of the select gates. The timing of the ramp down of the selected word line depends on whether it is among the predefined subset or the remaining subset. The predefined subset can include a number of adjacent or non-adjacent word lines.
摘要翻译：通过控制字线的幅度和时序并在感测操作结束时选择栅极斜坡下降电压，在3D存储器件中减少了由于热电子注入引起的读取干扰。在示例性读取操作中，字线的预定义子集包括源侧和漏极字线。对于字线的预定义子集，字线电压在选择门的电压下降之前下降。随后，对于字线的剩余子集，字线电压下降，但不迟于选择栅极的电压的斜降。所选字线的斜坡下降的时间取决于它是否在预定义的子集或剩余子集之间。预定义子集可以包括多个相邻或不相邻的字线。

5. 发明授权

US07869284B1 Erasing method for nonvolatile memory 有权
标题翻译：非易失性存储器的擦除方法
公开(公告)号：US07869284B1
公开(公告)日：2011-01-11
申请号：US12498010
申请日：2009-07-06
申请人： Ting-Chang Chang , Fu-Yen Jian , Hung-Wei Li
发明人： Ting-Chang Chang , Fu-Yen Jian , Hung-Wei Li
IPC分类号： G11C11/04
CPC分类号： G11C16/14 , G11C16/0408
摘要： The present invention relates to an erasing method for nonvolatile memory, which uses forward bias between the source/drain region and body contact to inject majority carriers into the body, and then accelerates the majority carriers by an electric field between the body and the gate to energize the majority carriers to overcome the oxide barrier and to erase the nonvolatile memory.
摘要翻译：本发明涉及一种用于非易失性存储器的擦除方法，其使用源极/漏极区域和体接触之间的正向偏压将多数载流子注入到体内，然后通过体和门之间的电场加速多数载流子，激励多数载流子以克服氧化物屏障并擦除非易失性存储器。

6. 发明授权

US07773422B2 3-level non-volatile semiconductor memory device and method of driving the same 有权
标题翻译： 3级非易失性半导体存储器件及其驱动方法
公开(公告)号：US07773422B2
公开(公告)日：2010-08-10
申请号：US12052666
申请日：2008-03-20
申请人： Ki-Tae Park , Jung-Dal Choi , Sung-Kyu Jo
发明人： Ki-Tae Park , Jung-Dal Choi , Sung-Kyu Jo
IPC分类号： G11C11/04
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/24
摘要： A page buffer for a non-volatile semiconductor memory device includes a switch configured to couple a first bitline coupled to a first memory cell to a second bitline coupled to a second memory cell, a first latch block coupled to the first bitline and configured to transfer a first latch data to the first memory cell, and a second latch block coupled to the second bitline and the first latch block, and configured to transfer a second latch data to the second memory cell.
摘要翻译：用于非易失性半导体存储器件的页面缓冲器包括被配置为将耦合到第一存储器单元的第一位线耦合到耦合到第二存储器单元的第二位线的开关，耦合到第一位线并被配置为传送的第一锁存块向第一存储器单元提供第一锁存数据，以及耦合到第二位线和第一锁存块的第二锁存块，并且被配置为将第二锁存数据传送到第二存储器单元。

7. 发明授权

US4593209A Read head for Wiegand Wire 失效
标题翻译：阅读Wiegand Wire的头
公开(公告)号：US4593209A
公开(公告)日：1986-06-03
申请号：US613635
申请日：1984-05-24
申请人： Carroll D. Sloan
发明人： Carroll D. Sloan
IPC分类号： G01R33/02 , G06K7/08 , G11C11/04 , H03K3/45
CPC分类号： G06K7/087 , G01R33/02 , G06K7/083
摘要： A read head for a Wiegand Wire has a low reluctance core on which a pick-up coil is wound. The Wiegand Wires are passed over a face of the core and coil and switch state directly over the core and coil so that the change in the magnetic field is coupled to the coil to produce an output pulse. Outboard of the direction in which the Wiegand Wires travels are first and second magnets that generate the field. In contact with these magnets and bridging both sides of the coil are first and second magnetic shunt members which control and determine the shape of the field. A first magnetic shunt member has a relatively narrow bridge portion which saturates under the field involved and thus there is a large leakage field adjacent to the face of the read head for the purpose of appropriately setting the Wiegand Wires. The second shunt has a much larger bridge portion so that there is much less leakage flux. However this smaller leakage flux is in the opposite direction from the leakage flux from the first shunt. The leakage flux from the second shunt serves to establish, accordingly, a negative field having a magnitude sufficient to reset the Wiegand Wire. In this fashion the two magnets and two shunts determine the strength and configuration of the field.
摘要翻译： Wiegand Wire的读头具有低磁阻芯，其上缠绕有拾音线圈。 Wiegand线通过芯线和线圈的面，并直接通过芯线圈和线圈开关状态，使得磁场的变化耦合到线圈以产生输出脉冲。威格导线行进方向的外侧是产生场的第一和第二磁体。与这些磁体接触并桥接线圈的两侧是控制和确定场的形状的第一和第二磁分路构件。第一磁分路构件具有相对窄的桥接部分，其在所涉及的磁场下饱和，因此为了适当地设置韦根电线，存在与读取头的表面相邻的大的泄漏场。第二分路具有更大的桥接部分，使得漏电流更少。然而，较小的漏磁通量与来自第一分流器的漏磁通相反。因此，来自第二分路的漏磁通用于建立具有足以复位韦根线的幅度的负磁场。以这种方式，两个磁铁和两个分流器确定了该领域的强度和配置。

8. 发明授权

US3863233A Magnetic memory array 失效
标题翻译：磁记忆阵列
公开(公告)号：US3863233A
公开(公告)日：1975-01-28
申请号：US34431673
申请日：1973-03-23
申请人： GOODYEAR AEROSPACE CORP
发明人： EDDEY EVERETT E , FAVOR JAMES N , MEILANDER WILLARD C
IPC分类号： G06F15/80 , G11C15/02 , G11C11/04 , G11C11/14
CPC分类号： G11C15/02 , G06F15/8038
摘要： An associative processor is provided which is a digital computer system capable of operating upon many independent sets of data at once or simultaneously. Each data set is processed sequentially, bit by bit giving an overall effect that is analogous to a large bank of serial computers all executing the same program, but on different data. Each memory word corresponds to one such serial processor. Since the available number of memory words greatly exceeds the number of data bits typically processed in parallel by a conventional sequential computer, the associative processor has a considerable speed advantage. Each word in memory has a common response store and arithmetic unit to accomplish logical operations in a parallel by word serial by bit interrogation. In essence, the processor combines an associative memory with control of the associative memory provided through essentially parallel input-output busses, and with the associative memory array incorporating arithmetic and logic circuits. These logic circuits permit parallel by word, serial by bit readout, thus incorporating an input/output capability that exceeds all prior computer techniques.
摘要翻译：提供了一种联合处理器，其是能够一次或同时地操作许多独立数据集的数字计算机系统。每个数据集被顺序地处理，逐位地给出类似于所有执行相同程序但是在不同数据上的大量串行计算机的整体效果。每个存储器字对应于一个这样的串行处理器。由于可用的存储器字数大大超过常规顺序计算机通常并行处理的数据位的数量，所以关联处理器具有相当大的速度优势。存储器中的每个单词具有通用的响应存储器和算术单元，以逐个逐位询问的方式并行地完成逻辑操作。本质上，处理器将关联存储器与通过基本上并行的输入 - 输出总线提供的关联存储器的控制以及结合算术和逻辑电路的关联存储器组合。这些逻辑电路允许通过字逐行读取并行，从而结合超过所有先前的计算机技术的输入/输出能力。

9. 发明授权

US3696506A Method of making a memory plane with powdered keepered material 失效
标题翻译：用粉状保存材料制作记忆板的方法
公开(公告)号：US3696506A
公开(公告)日：1972-10-10
申请号：US3696506D
申请日：1970-11-16
申请人： THOMAS & BETTS CORP
发明人： SINCLAIR WILLIAM Y
IPC分类号： G11C11/04 , H01F7/06
CPC分类号： G11C11/04 , Y10T29/49069
摘要： A memory plane includes a keepered word line structure formed by two cooperating molded assemblies, both having recesses for accommodating loose particles of magnetically conductive, but electrically non-conductive material. A contoured word strap assembly is partially disposed in each of said molded assemblies, after which the molded assemblies are joined together whereby the peaks of the contoured word strap assemblies define tunnels in which magnetically coated wires may be inserted, thereby completing the construction of the keepered memory plane.
摘要翻译：存储器平面包括由两个协作的模制组件形成的保持字线结构，两个配合的模制组件都具有用于容纳导磁的但不导电的材料的松散颗粒的凹部。一个轮廓字形带组合件部分地设置在每个所述模制组件中，之后模制组件被连接在一起，由此轮廓字形组件的顶点限定了可以插入磁性涂层的电线的隧道，从而完成了保持架记忆平面

10. 发明授权

US3685145A Method of making a batch fabricated magnetic wire memory 失效
标题翻译：制造批量制造的磁条存储器的方法
公开(公告)号：US3685145A
公开(公告)日：1972-08-22
申请号：US3685145D
申请日：1969-10-08
申请人： BUNKER RAMO
发明人： SCARBROUGH ALFRED D
IPC分类号： G11C11/155 , G11C5/02 , G11C5/04 , G11C11/04 , H01F7/06
CPC分类号： G11C5/04 , G11C5/02 , G11C11/04 , Y10T29/49069
摘要： A magnetic wire memory construction and method of making in which the memory comprises a plurality of stacked memory planes having memory wires inserted in aligned holes thereof. Each memory plane is fabricated using precision batch fabricated selective chemical etching techniques on a single self-supporting metal sheet so as to form pairs of insulated drive lines within the sheet looping around respective rows of a row-column matrix of memory wire receiving holes. Additional metal and magnetic layers may be provided over the surfaces of the sheets for increasing shielding and reducing memory cell disturbances.

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