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1. 发明授权

US11601133B2 System and method of performing discrete frequency transform for receivers using single-bit analog to digital converters 有权
公开(公告)号：US11601133B2
公开(公告)日：2023-03-07
申请号：US17081707
申请日：2020-10-27
申请人： Silicon Laboratories Inc.
发明人： Anant Verma
IPC分类号： H03M1/00 , H03M1/10 , H03M1/12 , G06F7/50 , G06F7/49 , G06F7/523 , G06F7/72
摘要： A system and method for performing discrete frequency transform including a pair of single-bit analog to digital converters (ADCs), a phase converter, a memory, a discrete frequency transform converter and summation circuitry. The ADCs convert an analog input signal into N pairs of binary in-phase and quadrature component samples each being one of four values at a corresponding one of four phases. The phase converter determines a phase value for each pair of component samples. The memory stores a set of discrete frequency transform coefficient values based on N. The discrete frequency transform converter uses a phase value and a pair of discrete frequency transform coefficient values retrieved from the memory for a selected frequency bin to determine a discrete frequency component for each pair of phase component samples. The summation circuitry sums the corresponding N frequency domain components for determining a frequency domain value for the selected frequency bin.

2. 发明申请

US20200159492A1 HIGH PERFORMANCE MERGE SORT WITH SCALABLE PARALLELIZATION AND FULL-THROUGHPUT REDUCTION 审中-公开
公开(公告)号：US20200159492A1
公开(公告)日：2020-05-21
申请号：US16688055
申请日：2019-11-19
申请人： Carnegie Mellon University
发明人： Fazle Sadi , Larry Pileggi , Franz Franchetti
IPC分类号： G06F7/16 , G06F7/49 , G06F7/499 , G06F9/30 , G06F9/54 , G06F16/901
摘要： Disclosed herein is a novel multi-way merge network, referred to herein as a Hybrid Comparison Look Ahead Merge (HCLAM), which incurs significantly less resource consumption as scaled to handle larger problems. In addition, a parallelization scheme is disclosed, referred to herein as Parallelization by Radix Pre-sorter (PRaP), which enables an increase in streaming throughput of the merge network. Furthermore, high performance reduction scheme is disclosed to achieve full throughput.

3. 发明申请

US20200150929A1 NATIVE TERNARY RANDOM NUMBERS GENERATION 审中-公开
公开(公告)号：US20200150929A1
公开(公告)日：2020-05-14
申请号：US16492581
申请日：2018-07-27
申请人： Arizona Board of Regents on Behalf of Northern Arizona University
发明人： Bertrand Francis Cambou
IPC分类号： G06F7/58 , H04L9/32 , G06F7/49
摘要： A system and method for random number generation are presented. A plurality of parameter values are generated by inspecting a plurality of cells in a memory array. Each parameter value in the plurality of parameter values is associated with a cell of the plurality of cells. A plurality of unstable cells in the plurality of cells are identified. Each unstable cell in the plurality of unstable cells is associated with a parameter value within a threshold value of an average of the plurality of parameter values. First, second and third groups of cells in the plurality of unstable cells identified and associated with values. The groups are determined based upon the parameter values associated with the cells in each group. A data stream is generated using the first group of cells, the second group of cells, and the third group of cells.

4. 发明申请

US20200081688A1 SPECULATIVE CALCULATIONS IN SQUARE ROOT OPERATIONS 审中-公开
公开(公告)号：US20200081688A1
公开(公告)日：2020-03-12
申请号：US16123236
申请日：2018-09-06
申请人： Arm Limited
发明人： Javier Diaz BRUGUERA
IPC分类号： G06F7/552 , G06F7/499 , G06F7/49
摘要： A data processing apparatus is provided that includes input circuitry to receive a signal corresponding to a square root instruction that identifies an input value. Processing circuitry performs an iterative square root operation on the input value and includes digit determination circuitry to determine, for a current iteration, a next digit of an least partial result of the square root operation and remainder determination circuitry that determines, for the current iteration, an at least partial remainder of the square root operation. The next digit for the current iteration is determined based on an least partial remainder of the square root operation from a previous iteration. The at least partial remainder for the current iteration is determined based on the at least partial remainder and the at least partial result of the square root operation from the previous iteration and the processing circuitry is adapted to speculatively generate a set of candidate at least partial remainders of the square root operation for the current iteration prior to the at least partial result of the square root operation for the current iteration being determined.

5. 发明授权

US10489154B2 Apparatus and method for complex multiply and accumulate 有权
公开(公告)号：US10489154B2
公开(公告)日：2019-11-26
申请号：US15824324
申请日：2017-11-28
申请人： Intel Corporation
发明人： Robert Valentine , Mark Charney , Raanan Sade , Elmoustapha Ould-Ahmed-Vall , Jesus Corbal , Roman S. Dubtsov
IPC分类号： G06F7/49 , G06F9/302 , G06F9/22 , G06F9/30 , G06F9/38 , G06F7/48 , G06F9/345
CPC分类号： G06F9/3001 , G06F9/3013 , G06F9/3016 , G06F7/4806 , G06F7/4812 , G06F9/30163 , G06F9/30167 , G06F9/345 , G06F9/382 , G06F9/3824
摘要： An embodiment of the invention is a processor including execution circuitry to calculate, in response to a decoded instruction, a result of a complex multiply-accumulate of a first complex number, a second complex number, and a third complex number. The calculation includes a first operation to calculate a first term of a real component of the result and a first term of the imaginary component of the result. The calculation also includes a second operation to calculate a second term of the real component of the result and a second term of the imaginary component of the result. The processor also includes a decoder to decode an instruction to generate the decoded instruction and a first source register, a second source register, and a source and destination register to provide the first complex number, the second complex number, and the third complex number, respectively.

6. 发明申请

US20190018653A1 MULTIPLY-ADD OPERATIONS OF BINARY NUMBERS IN AN ARITHMETIC UNIT 审中-公开
公开(公告)号：US20190018653A1
公开(公告)日：2019-01-17
申请号：US15649406
申请日：2017-07-13
申请人： International Business Machines Corporation
发明人： Tina Babinsky , Michael Klein , Cedric Lichtenau , Silvia M. Mueller
IPC分类号： G06F7/544 , G06F7/49 , G06F5/01
CPC分类号： G06F7/5443 , G06F5/01 , G06F7/49
摘要： Disclosed herein is a computer implemented method for performing multiply-add operations of binary numbers P, Q, R, S, B in an arithmetic unit of a processor, the operation calculating a result as an accumulated sum, which equals to B+n×P×Q+m×R×S, where n and m are natural numbers. Further disclosed herein is an arithmetic unit configured to implement multiply-add operations of binary numbers P, Q, R, S, B comprising at least a first binary arithmetic unit for calculating an aligned high part result and a second binary arithmetic unit for calculating an aligned low part result of the multiply-add operations.

7. 发明授权

US10133552B2 Data storage method, ternary inner product operation circuit, semiconductor device including the same, and ternary inner product arithmetic processing program 有权
公开(公告)号：US10133552B2
公开(公告)日：2018-11-20
申请号：US14797104
申请日：2015-07-11
申请人： Renesas Electronics Corporation
发明人： Shunsuke Okumura
IPC分类号： G06F7/49
摘要： A data storage method includes storing a plurality of pieces of 2-bit wide ternary data in one word, each of the plurality of pieces of 2-bit wide ternary data indicating +1 when a first bit indicates a first value, indicating −1 when a second bit indicates the first value, and indicating 0 when both the first bit and the second bit indicate a second value.

8. 发明授权

US10095723B1 System and method for providing products and locations 有权
公开(公告)号：US10095723B1
公开(公告)日：2018-10-09
申请号：US15283543
申请日：2016-10-03
申请人： Harold T. Fogg
发明人： Harold T. Fogg
IPC分类号： G06F17/30 , G06F17/16 , G06F7/49 , G06F17/12 , G06Q10/08
摘要： A method is provided for converting a location code index to a product code value, comprising performing a step selected from the group consisting of: applying a mapping L2P to a location code index nL to provide a product code index nP and applying a function nP2vP to the product code index nP to provide a product code value vP; and applying a function nL2vL to a location code index nL to provide a location code value vL and applying a mapping L2P to the location code value vL to provide a product code value vP. A system is also provided for providing a product code P from a location code L, the system comprising: a processor; an input coupled to the processor and configured to receive the location code L; and a converter L2P operable to map the location code L to the product code P.

9. 发明授权

US09766858B2 Vector operands with component representing different significance portions 有权
公开(公告)号：US09766858B2
公开(公告)日：2017-09-19
申请号：US14582968
申请日：2014-12-24
申请人： ARM Limited
发明人： David Raymond Lutz , Neil Burgess , Christopher Neal Hinds
IPC分类号： G06F9/30 , G06F7/48 , G06F9/38 , G06F11/34 , G06F11/36 , G06F7/38 , G06F17/16 , G06F5/01 , G06F7/483 , G06F7/499 , H03M7/12 , H03M7/24 , G06F7/507 , G06F7/49 , G06F7/50 , G06F7/12 , G06F7/24 , G06F7/506
CPC分类号： G06F7/483 , G06F5/012 , G06F7/38 , G06F7/48 , G06F7/4991 , G06F7/49915 , G06F7/49921 , G06F7/49942 , G06F7/506 , G06F7/507 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30036 , G06F9/30112 , G06F9/3016 , G06F9/30185 , G06F9/30192 , G06F9/3885 , G06F11/3404 , G06F11/3476 , G06F11/348 , G06F11/3636 , G06F11/3644 , G06F11/3648 , G06F17/16 , G06F2201/865 , G06F2207/483 , H03M7/12 , H03M7/24
摘要： A data processing system supports vector operands with components representing different bit significance portions of an integer number. Processing circuitry performs a processing operation specified by a program instruction in dependence upon a number of components comprising the vector as specified by metadata for the vector.

10. 发明申请

US20160283196A1 COMBINED ADDER AND PRE-ADDER FOR HIGH-RADIX MULTIPLIER CIRCUIT 有权
标题翻译：用于高分辨率多路复用器电路的组合添加器和预加器
公开(公告)号：US20160283196A1
公开(公告)日：2016-09-29
申请号：US14669288
申请日：2015-03-26
申请人： Altera Corporation
发明人： Martin Langhammer
IPC分类号： G06F7/49 , G06F7/501
CPC分类号： G06F7/49 , G06F7/501 , G06F7/5312
摘要： Circuitry accepting a first input value and a second input value, and outputting (a) a first sum involving the first input value and the second input value, and (b) a second sum involving the first input value and the second input value, includes a first adder circuit, a second adder circuit, a compressor circuit and a preprocessing stage. The first input value and the second input value are input to the first adder circuit to provide the first sum. The first input value and the second input value are input to the preprocessing stage to provide inputs to the compressor circuit, which provides first and second compressed output signals which in turn are input to the second adder circuit to provide the second sum. The preprocessing stage may include circuitry to programmably zero the first input value, so that the first sum is programmably settable to the second input value.
摘要翻译：电路接受第一输入值和第二输入值，并且输出（a）涉及第一输入值和第二输入值的第一和，以及（b）涉及第一输入值和第二输入值的第二和，包括第一加法器电路，第二加法器电路，压缩器电路和预处理级。第一输入值和第二输入值被输入到第一加法器电路以提供第一和。第一输入值和第二输入值被输入到预处理级以向压缩器电路提供输入，该压缩器电路提供第一和第二压缩输出信号，该压缩输出信号又被输入到第二加法器电路以提供第二和。预处理阶段可以包括可编程地将第一输入值归零的电路，使得第一和可编程地设置为第二输入值。

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