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1. 发明授权

US10929101B2 Processor with efficient arithmetic units 有权
公开(公告)号：US10929101B2
公开(公告)日：2021-02-23
申请号：US16056115
申请日：2018-08-06
申请人： Texas Instruments Incorporated
发明人： Christian Wiencke , Armin Stingl
IPC分类号： G06F7/44 , G06F7/53 , G06F7/42
摘要： A processor includes a carry save array multiplier. The carry save array multiplier includes an array of cascaded partial product generators. The array of cascaded partial product generators is configured to generate an output value as a product of two operands presented at inputs of the multiplier. The array of cascaded partial product generators is also configured to generate an output value as a sum of two operands presented at inputs of the multiplier.

2. 发明授权

US10658783B2 Mechanism for securing a module inserted into a module receiving frame to the module receiving frame 有权
公开(公告)号：US10658783B2
公开(公告)日：2020-05-19
申请号：US16168909
申请日：2018-10-24
申请人： ODU GmbH & Co. KG
发明人： Dominik Weichselgartner
IPC分类号： H01R13/60 , H01R13/518 , G01R31/28 , G01R31/00 , G06F7/42 , H01R13/74 , G01R1/04
摘要： A mechanism (4) for securing a module (5) inserted into a module receiving frame (1) to the module receiving frame (1) and releasing the module (5) for removal from the module receiving frame (1), comprising a catch (6) arranged on the module (5) or the module receiving frame (1), which catch (6) may be moved to and fro between an open position and a locking position of the catch (6), and a spring (7) for preloading the catch (6) into one of the two positions, the open position or the locking position. The mechanism (4) further comprises a catch holder (11), which may be moved to and fro between a retaining position, in which it holds the catch (6) back against the preloading of the spring (7), and a release position, in which it does not hold the catch (6) back against the preloading of the spring (7).

3. 发明授权

US10055195B2 Variable precision floating-point adder and subtractor 有权
公开(公告)号：US10055195B2
公开(公告)日：2018-08-21
申请号：US15270495
申请日：2016-09-20
申请人： Altera Corporation
发明人： Martin Langhammer
IPC分类号： G06F7/42 , G06F7/50 , G06F5/01
CPC分类号： G06F7/50 , G06F5/012 , G06F7/4912 , G06F2205/00 , G06F2207/3816 , G06F2207/48
摘要： An integrated circuit may include a floating-point adder that supports variable precisions. The floating-point adder may receive first and second inputs to be added, where the first and second inputs each have a mantissa and an exponent. The mantissa and exponent values may be split into a near path and a far path using a dual path floating-point adder architecture depending on the difference of the exponents and on whether an addition or subtraction is being performed. The mantissa values may be left justified, while the sticky bits are right justified. The hardware for the largest mantissa can be used to support the calculations for the smaller mantissas using no additional arithmetic structures, with only some multiplexing and decoding logic.

4. 发明授权

US08903881B2 Arithmetic circuit, arithmetic processing apparatus and method of controlling arithmetic circuit 有权
标题翻译：算术电路，运算处理装置及运算电路的控制方法
公开(公告)号：US08903881B2
公开(公告)日：2014-12-02
申请号：US13437969
申请日：2012-04-03
申请人： Ryuji Kan , Hideyuki Unno , Kenichi Kitamura
发明人： Ryuji Kan , Hideyuki Unno , Kenichi Kitamura
IPC分类号： G06F7/42 , G06F7/483 , G06F7/499
CPC分类号： G06F7/49942 , G06F7/483
摘要： An arithmetic circuit for quantizing pre-quantized data includes a first input register to store first-format pre-quantized data that includes a mantissa and an exponent, a second input register to store a quantization target exponent, an exponent-correction-value indicating unit to indicate an exponent correction value, an exponent generating unit to generate a quantized exponent obtained by subtracting the exponent correction value from the quantization target exponent, a shift amount generating unit to generate a shift amount obtained by subtracting the exponent of the pre-quantized data and the exponent correction value from the quantization target exponent, a shift unit to generate a quantized mantissa obtained by shifting the mantissa of the pre-quantized data by the shift amount generated by the shift amount generating unit, and an output register to store quantized data that includes the quantized exponent generated by the exponent generating unit and the quantized mantissa generated by the shift unit.
摘要翻译：用于量化预量化数据的算术电路包括：第一输入寄存器，用于存储包括尾数和指数的第一格式的预量化数据;存储量化目标指数的第二输入寄存器;指数校正值指示单元指示指数校正值，指数生成单元，用于生成通过从量化目标指数中减去指数校正值而获得的量化指数;移位量生成单元，生成通过减去预量化数据的指数得到的移位量以及来自量化目标指数的指数校正值，用于生成通过将预量化数据的尾数偏移由移位量产生单元生成的移位量而获得的量化尾数的移位单元和用于存储量化数据的输出寄存器其包括由指数生成单元生成的量化指数和量化的尾数gen 由换档单元擦除。

5. 发明授权

US08788561B2 Arithmetic circuit, arithmetic processing apparatus and method of controlling arithmetic circuit 失效
标题翻译：算术电路，运算处理装置及运算电路的控制方法
公开(公告)号：US08788561B2
公开(公告)日：2014-07-22
申请号：US13441020
申请日：2012-04-06
申请人： Ryuji Kan , Hideyuki Unno , Kenichi Kitamura
发明人： Ryuji Kan , Hideyuki Unno , Kenichi Kitamura
IPC分类号： G06F7/42
CPC分类号： G06F7/483 , G06F7/49942
摘要： An arithmetic circuit calculates a correction value for a value that is obtained by an add-subtract operation of two values and that is expressed in a predetermined fixed precision.
摘要翻译：算术电路计算通过两个值的加减运算获得的并以预定的固定精度表示的值的校正值。

6. 发明授权

US08620983B2 Leading sign digit predictor for floating point near subtractor 有权
标题翻译：浮点附近减法器的前导符号数字预测器
公开(公告)号：US08620983B2
公开(公告)日：2013-12-31
申请号：US12985180
申请日：2011-01-05
申请人： Tom Elmer
发明人： Tom Elmer
IPC分类号： G06F7/42 , G06F7/00
CPC分类号： G06F7/485
摘要： An apparatus for predicting leading sign digits in a negative difference includes a comparator that determines a larger of two numbers that differ in magnitude by not more than one digit position. The larger of the two numbers is designated as the subtrahend and the smaller as the minuend. Wires and logic align the subtrahend relative to the minuend by the not more than one digit position and invert the aligned subtrahend. A plurality of NAND gates performs a Boolean NAND function of corresponding digits of the minuend and the aligned inverted subtrahend to produce a prediction string of bits. A zero value is assigned to the most significant bit of the prediction string. A string of leading zeros of the prediction string predicts a corresponding string of leading sign digits of a negative difference of the minuend and aligned subtrahend.
摘要翻译：用于以负差预测前导符号数字的装置包括比较器，其确定大小不同不超过一个数字位置的两个数字中较大的数字。两个数字中的较大的数字被指定为减数，小数被指定为被减数。电线和逻辑将减法相对于限制器对齐不超过一个数字位置，并反转对准的减法器。多个NAND门执行微处理器和对齐的反向减法相关数字的布尔NAND功能，以产生位的预测串。零值被分配给预测串的最高有效位。预测串的前导零的一串预测了一个对应的引导符号数字串，该位数是减法和对齐的减法的负差值。

7. 发明申请

US20130117341A1 DECIMAL ELEMENTARY FUNCTIONS COMPUTATION 失效
标题翻译： DECIMAL ELEMENTARY功能计算
公开(公告)号：US20130117341A1
公开(公告)日：2013-05-09
申请号：US13293061
申请日：2011-11-09
申请人： Tarek Eldeeb , Hossam Aly Hassan Fahmy , Mahmoud Y. Hassan
发明人： Tarek Eldeeb , Hossam Aly Hassan Fahmy , Mahmoud Y. Hassan
IPC分类号： G06F7/42 , G06F7/44
CPC分类号： G06F7/544 , G06F2207/4911
摘要： A method for executing a decimal elementary function (DEF) computation from multiple decimal floating-point operands, including: extracting mantissae and exponents from the operands; generating normalized mantissae by shifting the mantissae based on the number of leading zeros; calculating a plurality of approximations for a logarithm of the first normalized mantissa; calculating, using the plurality of approximations for the logarithm, a plurality of approximations for a product of the second normalized mantissa and a sum based on the logarithm of the first normalized mantissa and an exponent; generating a plurality of shifted values by shifting the plurality of approximations for the product; generating a plurality of fraction components from the plurality of shifted values; calculating an antilog based on the plurality of fraction components; and outputting a decimal floating-point result of the DEF computation comprising a resultant mantissa based on the antilog and a resultant biased exponent.
摘要翻译：一种用于从多个十进制浮点运算执行十进制基本函数（DEF）计算的方法，包括：从操作数中提取出mantissae和exponents; 通过基于前导零的数量移动镰刀生成归一化的镰刀; 计算第一标准化尾数的对数的多个近似值; 使用所述对数的所述近似来计算所述第二标准化尾数与基于所述第一标准化尾数和指数的对数的乘积的乘积的多个近似; 通过移动产品的多个近似来产生多个移位值; 从所述多个移位值生成多个分数分量; 基于多个分数分量计算反对数; 并输出DEF运算的十进制浮点运算结果，该结果包括基于反序号和合成偏移指数的合成尾数。

8. 发明授权

US08185570B2 Three-term input floating-point adder-subtractor 失效
标题翻译：三项输入浮点加减法器
公开(公告)号：US08185570B2
公开(公告)日：2012-05-22
申请号：US11955571
申请日：2007-12-13
申请人： Yusuke Fukumura , Patrick Hamilton , Masaya Nakahata , Takashi Oomori
发明人： Yusuke Fukumura , Patrick Hamilton , Masaya Nakahata , Takashi Oomori
IPC分类号： G06F7/42 , G06F7/50 , G06F11/00
CPC分类号： G06F7/485 , G06F7/49963
摘要： The adder-subtractor includes a pre-processing circuit which divides three inputted terms into a mantissa having an exponent of maximum value, mantissa having an exponent of intermediate value and mantissa having an exponent of minimum magnitude and outputting a mantissa obtained by right-shifting the mantissa having the exponent of intermediate value and the mantissa having the minimum exponent of 2n+3 bits and adjusting digits and the mantissa having the maximum exponent, which reduces the mantissas from three to two terms, which carries out addition on the mantissas of the two terms, a normalization circuit which makes left shift so that the most significant bit becomes 1, a rounding circuit which uses an (n+3)th bit from the most significant bit as a new sticky bit, takes logical OR with the lower bits and performs rounding and an exponent operation unit which outputs a final exponent.
摘要翻译：加法器 - 减法器包括预处理电路，其将三个输入的项分成具有最大值的指数的尾数，具有中间值指数的尾数和具有最小幅度指数的尾数，并输出通过右移所获得的尾数具有中值的指数的尾数和具有2n + 3位的最小指数的尾数，并且调整数字和具有最大指数的尾数，这将尾数从三个字节减少到两个项，这在两个字符的尾数上执行加法使得使最高有效位变为1的左移的归一化电路，使用来自最高有效位的第（n + 3）位作为新的粘性位的舍入电路与较低位进行逻辑或，执行舍入和指数运算单元，其输出最终指数。

9. 发明授权

US08069200B2 Apparatus and method for implementing floating point additive and shift operations 失效
标题翻译：实现浮点添加剂和换档操作的装置和方法
公开(公告)号：US08069200B2
公开(公告)日：2011-11-29
申请号：US11380613
申请日：2006-04-27
申请人： George Landers , Earle Jennings
发明人： George Landers , Earle Jennings
IPC分类号： G06F7/38 , G06F7/42 , G06F7/44 , H04N7/12 , H04N11/02 , H04N11/04
CPC分类号： G06F7/485 , G06F5/012
摘要： A floating point (FP) shifter for use with FP adders providing a shifted FP operand as a power of the exponent base (usually two) multiplied by a FP operand. First arithmetic processor using at least one FP shifter with FP adder. FP adder for N FP operands creating FP result, where N is at least three. Second arithmetic processor including at least one FP adder for N operands. Descriptions of FP shifter and FP adder for implementing their operational methods. Implementations of FP shifter and FP adder.
摘要翻译：与FP加法器一起使用的浮点（FP）移位器，提供移位的FP操作数作为指数基数（通常为2）乘以FP操作数的幂。使用FP加法器的至少一个FP移位器的第一算术处理器。 FP加法器，用于产生FP结果的N个FP操作数，其中N至少为3。第二运算处理器包括用于N个操作数的至少一个FP加法器。 FP移位器和FP加法器的描述，用于实现其操作方法。 FP移位器和FP加法器的实现。

10. 发明申请

US20100235414A1 Scalable Montgomery Multiplication Architecture 有权
标题翻译：可扩展的蒙哥马利乘法架构
公开(公告)号：US20100235414A1
公开(公告)日：2010-09-16
申请号：US12714992
申请日：2010-03-01
申请人： Miaoqing Huang , Krzysztof Gaj
发明人： Miaoqing Huang , Krzysztof Gaj
IPC分类号： G06F7/44 , G06F5/01 , G06F7/72 , G06F7/42
CPC分类号： G06F7/728
摘要： A Montgomery multiplication device calculates a Montgomery product of an operand X and an operand Y with respect to a modulus M and includes a plurality of processing elements. In a first clock cycle, two intermediate partial sums are created by obtaining an input of length w−1 from a preceding processing element as w−1 least significant bits. The most significant bit is configured as either zero or one. Then, two partial sums are calculated using a word of the operand Y, a word of the modulus M, a bit of the operand X, and the two intermediate partial sums. In a second clock cycle, a selection bit is obtained from a subsequent processing element and one of the two partial sums is selected based on the value of the selection bit. Then, the selected partial sum is used for calculation of a word of the Montgomery product.
摘要翻译：蒙哥马利乘法装置相对于模数M计算操作数X和操作数Y的蒙哥马利乘积，并且包括多个处理要素。在第一时钟周期中，通过从前一处理元件获得长度w-1的输入作为w-1个最低有效位来创建两个中间部分和。最高有效位被配置为零或一。然后，使用操作数Y的字，模M的字，操作数X的位和两个中间部分和来计算两个部分和。在第二时钟周期中，从后续处理元件获得选择位，并且基于选择位的值选择两个部分和之一。然后，所选择的部分和用于计算蒙哥马利产品的单词。

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