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1. 发明授权

US6133146A Semiconductor bridge device and method of making the same 失效
标题翻译：半导体桥式器件及其制造方法
公开(公告)号：US6133146A
公开(公告)日：2000-10-17
申请号：US644008
申请日：1996-05-09
申请人： Bernardo Martinez-Tovar , John A. Montoya
发明人： Bernardo Martinez-Tovar , John A. Montoya
IPC分类号： B81B3/00 , F42B3/13 , H07L21/44
CPC分类号： F42B3/13
摘要： A device, e.g., an explosive-initiation device (24) includes a semiconductor bridge device (10) comprising semiconductor pads (14a, 14b) separated by an initiator bridge (14c) and having metallized lands (16a, 16b) disposed over the pads (14a, 14b). The metallized lands (16a, 16b) each comprise a titanium base layer (18), a titanium-tungsten intermediate layer (20) and a tungsten top layer (22). This multilayer construction is simple to apply, provides good adhesion to the semiconductor (14) and enhanced semiconductor bridge characteristics, and avoids the electromigration problems attendant upon use of aluminum metallized lands under severe conditions of no-fire tests and very low firing voltage or current levels. The semiconductor (14) may optionally be covered by a cap or cover (117) of a stratified metal layer similar or identical to the metallized lands (16a, 16b). A method of making the semiconductor bridge devices includes metal sputtering of titanium, then titanium plus tungsten and then tungsten onto an appropriately masked semiconductor surface to attain the multilayer metallized lands (16a, 16b) and/or cover (117) of the invention.
摘要翻译：诸如爆炸物引发装置（24）的装置包括半导体桥接装置（10），其包括由引发器桥（14c）分开并且具有设置在焊盘上的金属化焊盘（16a，16b）的半导体焊盘（14a，14b）（14a，14b）。金属化焊盘（16a，16b）各自包括钛基层（18），钛 - 钨中间层（20）和钨顶层（22）。这种多层结构易于应用，提供对半导体（14）的良好粘附性和增强的半导体桥特性，并且避免了在苛刻的无火试验条件下以及极低的点火电压或电流下使用铝金属化焊盘时伴随的电迁移问题水平。半导体（14）可以可选地由与金属化焊盘（16a，16b）类似或相同的分层金属层的盖或盖（117）覆盖。制造半导体桥接器件的方法包括钛，然后钛加钨，然后钨到金属溅射到适当掩蔽的半导体表面上，以获得本发明的多层金属化焊盘（16a，16b）和/或盖（117）。

2. 发明授权

US6162706A Method of epitaxy on a silicon substrate comprising areas heavily doped with arsenic 失效
公开(公告)号：US6162706A
公开(公告)日：2000-12-19
申请号：US124825
申请日：1998-07-29
申请人： Didier Dutartre , Patrick Jerier
发明人： Didier Dutartre , Patrick Jerier
IPC分类号： C30B29/06 , C23C16/24 , C30B25/02 , C30B25/20 , H01L21/205 , H07L21/44
CPC分类号： C30B29/06 , C23C16/24 , C30B25/20
摘要： The present invention relates to a method of vapor phase epitaxial deposition of silicon on a silicon substrate including areas containing dopants at high concentration among which is arsenic, while avoiding an autodoping of the epitaxial layer by arsenic, including the steps of performing a first thin epitaxial deposition, then an anneal; the conditions and the duration of the first epitaxial deposition and of the anneal being such that the arsenic diffusion length is much lower than the thickness of the layer formed in the first deposition; and performing a second epitaxial deposition for a chosen duration to obtain a desired total thickness.

3. 发明授权

US6156651A Metallization method for porous dielectrics 失效
标题翻译：多孔电介质的金属化方法
公开(公告)号：US6156651A
公开(公告)日：2000-12-05
申请号：US988175
申请日：1997-12-10
申请人： Robert H. Havemann
发明人： Robert H. Havemann
IPC分类号： C23C14/04 , H01L21/28 , H01L21/306 , H01L21/768 , H01L23/522 , H01L23/532 , H07L21/44 , B44C1/22
CPC分类号： H01L21/76802 , H01L21/7682 , H01L21/76831 , H01L21/76841 , H01L21/76843 , H01L21/76865 , H01L21/76873 , H01L21/76874 , H01L21/76879 , H01L21/7688 , H01L23/5226 , H01L23/53223 , H01L23/53238 , H01L23/5329 , H01L2924/0002
摘要： This is a method of forming mechanically robust vias and entrenched conductors on a dielectric layer (which dielectric layer is on an electronic microcircuit substrate which vias and entrenched conductors are electrically connected to a conductive area on the surface of the substrate) and a structure formed thereby. Generally some of the dielectric layers added above the microcircuit comprise a porous dielectric having a desirable low dielectric constant but low mechanical robustness. Special methods are described which generally comprise: forming the dielectric layer over the substrate; forming a nanaporous dielectric layer over the substrate; depositing a planarizing stopping material over the top surface of said nanaporous dielectric; depositing and patterning photoresist; etching said stopping material and nanaporous dielectric layer in a conductor pattern to expose at least a portion of said conductive area on the surface of said substrate; depositing a wall seal; depositing conductor metal; and planarizing said structure. Generally the via metal and the conductor metal consist essentially of aluminum, copper or combinations thereof. The conductor metal may be doped with the selectively deposited via metal being doped by dopant diffusion from the conductor metal, thereby avoiding the difficulty of depositing a doped selective metal. Methods are shown for realizing desirable insulating and conducting layers without deleterious mechanical effects.
摘要翻译：这是一种在电介质层（介电层位于电子微电路基板上的通孔和固定的导体电连接到基板的表面上的导电区域）上形成机械坚固的通孔和根管的导体的方法，以及由此形成的结构。通常，微电路之上的一些电介质层包括具有期望的低介电常数但低机械坚固性的多孔电介质。描述了通常包括：在衬底上形成介电层的特殊方法; 在衬底上形成纳米电介质层; 在所述纳米电介质的顶表面上沉积平坦化止动材料; 沉积和图案化光刻胶; 以导体图形蚀刻所述停止材料和纳米电介质层，以暴露所述衬底表面上的所述导电区域的至少一部分; 沉积墙密封; 沉积导体金属; 并平坦化所述结构。通常，通孔金属和导体金属基本上由铝，铜或其组合组成。导体金属可以掺杂有选择性沉积的通孔金属，其通过掺杂剂从导体金属扩散掺杂，从而避免沉积掺杂的选择性金属的困难。示出了用于实现理想的绝缘和导电层而没有有害的机械效应的方法。

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