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1. 发明授权

US07433824B2 Entropy coding by adapting coding between level and run-length/level modes 有权
标题翻译：熵编码通过适应水平和游程长度/级别模式之间的编码
公开(公告)号：US07433824B2
公开(公告)日：2008-10-07
申请号：US10647923
申请日：2003-08-25
申请人： Sanjeev Mehrotra , Wei-ge Chen
发明人： Sanjeev Mehrotra , Wei-ge Chen
IPC分类号： H03M7/42 , H03M7/44 , G10L19/00 , H04B1/66
CPC分类号： G10L19/008 , G10L19/0017 , G10L19/02 , G10L19/0212 , G10L19/025 , G10L19/032 , G10L19/038 , G10L19/06 , G10L19/24 , G10L2015/025
摘要： An audio encoder performs adaptive entropy encoding of audio data. For example, an audio encoder switches between variable dimension vector Huffman coding of direct levels of quantized audio data and run-level coding of run lengths and levels of quantized audio data. The encoder can use, for example, context-based arithmetic coding for coding run lengths and levels. The encoder can determine when to switch between coding modes by counting consecutive coefficients having a predominant value (e.g., zero). An audio decoder performs corresponding adaptive entropy decoding.
摘要翻译：音频编码器执行音频数据的自适应熵编码。例如，音频编码器在量化音频数据的直接电平的可变维矢量霍夫曼编码和游程长度的游程级编码以及量化的音频数据的电平之间切换。编码器可以使用例如用于对运行长度和电平进行编码的基于上下文的算术编码。编码器可以通过计算具有主要值（例如，零）的连续系数来确定何时在编码模式之间切换。音频解码器执行相应的自适应熵解码。

2. 发明授权

US5909552A Method and apparatus for processing packed data 失效
标题翻译：用于处理打包数据的方法和装置
公开(公告)号：US5909552A
公开(公告)日：1999-06-01
申请号：US32764
申请日：1993-03-16
申请人： Allen Peter Jensen , Michael Terrell Vanover
发明人： Allen Peter Jensen , Michael Terrell Vanover
IPC分类号： G06F7/38 , G06F5/00 , G06F7/48 , G06F7/50 , G06F7/505 , G06F7/509 , G06T11/00 , H03M7/44
CPC分类号： G06F7/505 , G06F5/00 , G06F7/48 , G06F9/30036 , G06F2207/3828
摘要： A method and an apparatus for processing a plurality of operands in parallel including packing the operands into a word with at least one cleared buffer bit between each operand and processing the packed word.
摘要翻译：一种用于并行处理多个操作数的方法和装置，包括：将每个操作数之间的至少一个清除的缓冲器位与所述打包的字进行处理，以将操作数打包成一个字。

3. 发明授权

US5751233A Decoding apparatus and method therefor 失效
标题翻译：解码装置及其方法
公开(公告)号：US5751233A
公开(公告)日：1998-05-12
申请号：US644246
申请日：1996-05-10
申请人： Tetsuya Tateno , Yuji Minami
发明人： Tetsuya Tateno , Yuji Minami
IPC分类号： G06T9/00 , H03M7/42 , H03M7/44 , H04N1/419 , H03M7/40
CPC分类号： G06T9/005 , H03M7/425 , H04N1/419 , H04N19/13 , H04N19/91
摘要： A decoder decodes input codes, such as Modified Huffman, Modified READ, and Modified Modified READ codes, and includes a zero bit detector which detects the number of consecutive leading zero bits of the input code. An address compressor forms address data by performing a logical operation of data indicating the number of detected zero bits and data excluding the consecutive leading zero bits and the next one bit of the data. A reference table for code conversion is addressed by the formed address data from the address compressor and outputs decoded data corresponding to the input code.
摘要翻译：解码器对诸如Modified Huffman，Modified READ和Modified Modified READ码的输入代码进行解码，并且包括检测输入代码的连续前导零位数的零位检测器。地址压缩器通过执行表示检测到的零比特数的数据和除了连续前导零比特和数据的下一个比特之外的数据的逻辑运算来形成地址数据。通过来自地址压缩器的形成的地址数据来解决用于代码转换的参考表，并且输出与输入代码对应的解码数据。

4. 发明授权

US5553260A Apparatus for expanding compressed binary data 失效
标题翻译：扩展压缩二进制数据的装置
公开(公告)号：US5553260A
公开(公告)日：1996-09-03
申请号：US70121
申请日：1993-06-01
申请人： Toshiki Miyane
发明人： Toshiki Miyane
IPC分类号： H03M7/30 , G06T9/00 , H03M7/44 , H03M7/46 , G06F12/00
CPC分类号： H04N19/60 , H03M7/46
摘要： A data expansion apparatus that performs data expansion operation for a data block unit in a constant period of time is provided. First and second memory devices are first initialized by storing zeroes at all of their addresses. Numeric data and number-of-zeroes data (i.e., data representing the number of successive zeroes) are input to the data expansion apparatus. A calculation circuit outputs a calculated value by combining the number-of-zeroes data, a previous calculated value and 1 together. A first selection circuit associated with the first memory device selects the calculated value and numeric data and output them to the first memory device for storing the numeric data at the address specified by the calculated value. This operation is then repeated. After the first memory device completes the expansion operation, it is switched to perform read operation and the second memory device begins to perform expansion operation through second selection circuit in a similar manner. In performing the read operation by the first memory device, the first selection circuit selects the output of a read address generator and zeroes from a zerodata device and outputs them to the first memory device for reading out the data at the address specified by the output of the read address generator. At the same time, zeroes from the zero data device are input to the first memory device to replace those data which have been read out. This operation is then repeated. After the first memory device completes the read operation, it is switched back to perform expansion operation and the second memory device begins to perform read operation through the second selection circuit in a similar manner. Therefore, the data expansion operation is performed by alternately switching the operations performed by the first and second memory devices.
摘要翻译：提供了一种在一定时间段内对数据块单元执行数据扩展操作的数据扩展装置。第一和第二存储器件首先通过在其所有地址处存储零来初始化。数据数据和零数据数据（即表示连续零数的数据）被输入到数据扩展装置。计算电路通过将数字零数据，先前的计算值和1组合在一起来输出计算值。与第一存储器件相关联的第一选择电路选择计算值和数值数据，并将其输出到第一存储器件，用于将数值数据存储在由计算值指定的地址处。然后重复该操作。在第一存储器件完成扩展操作之后，切换为执行读取操作，并且第二存储器件以类似的方式开始通过第二选择电路执行扩展操作。在执行第一存储器件的读取操作时，第一选择电路选择读地址生成器的输出，并从零存储器件中选择零，并将其输出到第一存储器件，以读出由读地址生成器。同时，零数据设备的零被输入到第一存储器装置以替换已读出的数据。然后重复该操作。在第一存储器件完成读操作之后，切换回执行扩展操作，并且第二存储器件以类似的方式开始通过第二选择电路执行读操作。因此，通过交替切换由第一和第二存储器件执行的操作来执行数据扩展操作。

5. 发明授权

US07724827B2 Multi-layer run level encoding and decoding 有权
标题翻译：多层运行级编解码
公开(公告)号：US07724827B2
公开(公告)日：2010-05-25
申请号：US10826971
申请日：2004-04-15
申请人： Jie Liang , Chih-Lung Lin , Shankar Regunathan , Sridhar Srinivasan
发明人： Jie Liang , Chih-Lung Lin , Shankar Regunathan , Sridhar Srinivasan
IPC分类号： H03M7/44 , H03M7/40 , H03M7/48 , H04N7/26 , H03M7/46
CPC分类号： H04N19/93 , H04N19/102 , H04N19/109 , H04N19/11 , H04N19/112 , H04N19/117 , H04N19/129 , H04N19/13 , H04N19/137 , H04N19/146 , H04N19/147 , H04N19/159 , H04N19/16 , H04N19/172 , H04N19/176 , H04N19/18 , H04N19/184 , H04N19/186 , H04N19/196 , H04N19/46 , H04N19/463 , H04N19/51 , H04N19/52 , H04N19/523 , H04N19/593 , H04N19/61 , H04N19/63 , H04N19/70 , H04N19/82 , H04N19/86
摘要： Entropy coding and decoding techniques are described, which may be implemented separately or in combination. For example, a video encoder uses two-layer run level coding to reduce bitrate for frequency transform coefficients in a quick and efficient manner, and a video decoder uses corresponding two-layer run level decoding. This two-layer coding/decoding can be generalized to more than two layers of run level coding/decoding. The video encoder and decoder exploit common patterns in run level information to reduce code table size and create opportunities for early termination of decoding. Using zoned Huffman code tables helps limit overall table size while still providing a level of adaptivity in encoding and decoding. Using embedded Huffman code tables allows the encoder and decoder to reuse codes for 8×8, 8×4, 4×8, and 4×4 blocks.
摘要翻译：描述了熵编码和解码技术，其可以单独地或组合地实现。例如，视频编码器使用双层运行级编码以快速且有效的方式降低频率变换系数的比特率，并且视频解码器使用对应的双层运行级解码。这种双层编码/解码可以推广到两层以上的运行级编码/解码。视频编码器和解码器利用运行级信息中的常见模式来减少代码表大小，并为解码提早终止创造机会。使用分区霍夫曼代码表有助于限制整体表格大小，同时在编码和解码中仍然提供一定程度的适应性。使用嵌入式霍夫曼码表，编码器和解码器可以重用8×8,8×4,4×8,4×4块的码。

6. 发明授权

US4963867A Apparatus for packing parallel data words having a variable width into parallel data words having a fixed width 失效
标题翻译：用于将具有可变宽度的并行数据字打包成具有固定宽度的并行数据字的装置
公开(公告)号：US4963867A
公开(公告)日：1990-10-16
申请号：US331977
申请日：1989-03-31
申请人： Keith J. Bertrand
发明人： Keith J. Bertrand
IPC分类号： G06F5/00 , H03M7/44
CPC分类号： G06F5/00
摘要： The data packer receives n-bit wide parallel data words, and it outputs m-bit wide packed parallel data words, where n is a variable and may change during the operation, and m is a fixed integer. The input data words are applied to a bit shifter and therefrom to a data output circuit where they are stored until the necessary m bits are obtained. In the preferred embodiment a control circuit which comprises an adder, receives information indicating the number of valid data bits in each input word, and it provides a running sum of the number of received valid data bits. When the number of bits in an input word is equal to or greater than m, the control circuit provides a first control signal which occurs simultaneously with an m-bit wide packed parallel output word provided by the output circuit. Any number of input bits which is less than m is added to a remainder of a previous sum which is also less than m. When the thusly obtained sum is equal to or greater than m, a second control signal is provided which also occurs simultaneously with an m-bit wide packed word provided by the output circuit. The control circuit applies the running sum as a third control signal to the bit shifter, effecting shift of the next received data word by a number of bit positions corresponding to that sum. The number indicated by the third control signal also corresponds to the number of bits currently stored in the output circuit.

7. 发明授权

US4612532A Data compression apparatus and method 失效
标题翻译：数据压缩装置及方法
公开(公告)号：US4612532A
公开(公告)日：1986-09-16
申请号：US622547
申请日：1984-06-19
申请人： Francis L. Bacon , Donald J. Houde
发明人： Francis L. Bacon , Donald J. Houde
IPC分类号： H03M7/46 , H03M7/42 , H03M7/44 , H03M7/00
CPC分类号： H03M7/42
摘要： A preferred embodiment of the invention provides a system for the dynamic encoding of a stream of characters. In a preferred embodiment, the system includes an input for receiving a stream of characters, and an output for providing encoded data. The system also includes a provision for storing, accessing, and updating a table (what I call a "followset" table) for each of a plurality of characters, listing candidates for the character which may follow, in the stream, the character with which the table is associated. The system also includes a provision for furnishing at the output, for a given character in the stream at the input, a signal indicative of the position, occupied by the given character, in the followset character which immediately precedes the given character in the stream of the input. A preferred embodiment of the invention also provides a system for decoding the encoded data, wherein the decoder utilizes a followset table.
摘要翻译：本发明的优选实施例提供了一种用于字符流的动态编码的系统。在优选实施例中，系统包括用于接收字符流的输入端和用于提供编码数据的输出。该系统还包括用于存储，访问和更新表（对于多个字符中的每一个）的表（我称之为“后续”表）的规定，列出流中可能遵循的字符的候选，该表已关联。该系统还包括用于在输出处为输入中的流中的给定字符提供表示给定字符占据的位置的信号的规定，该信号紧跟在给定字符流中的给定字符之前的后续字符中输入。本发明的优选实施例还提供了一种用于对编码数据进行解码的系统，其中该解码器利用一个后续表。

8. 发明授权

US07469011B2 Escape mode code resizing for fields and slices 有权
标题翻译：退出模式代码调整字段和切片大小
公开(公告)号：US07469011B2
公开(公告)日：2008-12-23
申请号：US10933910
申请日：2004-09-02
申请人： Chih-Lung Lin , Pohsiang Hsu , Thomas W. Holcomb , Sridhar Srinivasan
发明人： Chih-Lung Lin , Pohsiang Hsu , Thomas W. Holcomb , Sridhar Srinivasan
IPC分类号： H04N7/26 , H03M7/40 , H03M7/48 , H03M7/42 , H03M7/44
CPC分类号： H04N19/93 , H04N19/102 , H04N19/109 , H04N19/11 , H04N19/112 , H04N19/117 , H04N19/129 , H04N19/13 , H04N19/137 , H04N19/146 , H04N19/147 , H04N19/159 , H04N19/16 , H04N19/172 , H04N19/176 , H04N19/18 , H04N19/184 , H04N19/186 , H04N19/196 , H04N19/46 , H04N19/463 , H04N19/51 , H04N19/52 , H04N19/523 , H04N19/593 , H04N19/61 , H04N19/63 , H04N19/70 , H04N19/82 , H04N19/86
摘要： Techniques and tools for escape mode code resizing are described. For example, a video decoder receives encoded information (e.g., runs, levels) for transform coefficients of blocks. For at least some of the encoded information, the decoder decodes in an escape mode for which codes have sizes signaled on a sub-frame basis (e.g., on a per-interlaced field basis in a video frame, or on a per-slice basis in a video frame). A video encoder performs corresponding encoding and signaling.
摘要翻译：描述了用于逃生模式代码调整大小的技术和工具。例如，视频解码器接收块的变换系数的编码信息（例如，运行，级别）。对于编码信息中的至少一些，解码器以一个逃逸模式进行解码，对于这些模式，代码具有以子帧为基础的信号大小（例如，以视频帧中的每个隔行扫描的字段为基础，或者以每片为单位）在视频帧中）。视频编码器执行相应的编码和信号。

9. 发明授权

US6069575A Variable length code decoder 失效
标题翻译：可变长度码解码器
公开(公告)号：US6069575A
公开(公告)日：2000-05-30
申请号：US92943
申请日：1998-06-08
申请人： Shigenori Kinouchi , Akira Sawada
发明人： Shigenori Kinouchi , Akira Sawada
IPC分类号： H03M7/42 , H03M7/44 , H04N1/41 , H04N19/00 , H04N19/13 , H04N19/134 , H04N19/42 , H04N19/423 , H04N19/44 , H04N19/46 , H04N19/625 , H04N19/70 , H04N19/91 , H03M7/40
CPC分类号： H03M7/425 , H04N19/423 , H04N19/60 , H04N19/61 , H04N19/91
摘要： To provide a VLC decoder having a decoding speed sufficiently high to be applicable for decoding MPEG 2 data, and having an appropriate circuit size to be integrated on an IC chip, a VLC decoder comprises: a first decode table (102) implemented with logic circuits for decoding a "zero-run code" at one clock; a second decode table (104) implemented on a memory device for decoding other VLC making use of a tree searching technique; a switching means (103, 105, 108) for switching from the first decode table (102) to the second decode table (104) when EOB code is decoded and switching from the second decode table (104) to the first decode table (102) when the "zero-run code" begins.
摘要翻译：为了提供具有足够高的解码速度的VLC解码器以适用于MPEG 2数据的解码，并且具有要集成在IC芯片上的适当的电路尺寸，VLC解码器包括：用逻辑电路实现的第一解码表（102）用于在一个时钟解码“零运行代码”; 在存储器装置上实现的第二解码表（104），用于使用树搜索技术解码其他VLC; 用于当EOB码被解码并从第二解码表（104）切换到第一解码表（102）时从第一解码表（102）切换到第二解码表（104）的切换装置（103,105,108））当“零运行代码”开始时。

10. 发明授权

US6049571A Encoding circuit with a function of zero continuous-suppression in a data transmission system 失效
标题翻译：在数据传输系统中具有零连续抑制功能的编码电路
公开(公告)号：US6049571A
公开(公告)日：2000-04-11
申请号：US208088
申请日：1998-12-09
申请人： Hitoshi Hasegawa , Makoto Adachi , Makoto Yamada
发明人： Hitoshi Hasegawa , Makoto Adachi , Makoto Yamada
IPC分类号： H03M7/44 , H04J3/00 , H04L25/34 , H04L25/49
CPC分类号： H04L25/4904
摘要： An encoding circuit with a function of zero continuous-suppression in a data transmission system according to the present invention includes an EXZ detecting unit, a NRZ pulse generating unit and an output control unit. The EXZ detecting unit receives serial data indicating a NRZ signal and binary information indicating a code rule, and outputs EXZ pulses and delay data. The NRZ pulse generating unit receives the EXZ pulses from the EXZ detecting unit, and outputs an EXZ detecting signal, bipolar rule pulses and violation pulses. The output control unit receives the EXZ detecting signal, the bipolar rule pulses and the violation pulses, these are output from the NRZ pulse generating unit, and the delay data from the EXZ detecting unit, and outputs P-pole pulses and N-pole pulses to an external stage, and an odd signal to the NRZ pulse generating unit.
摘要翻译：在根据本发明的数据传输系统中具有零连续抑制功能的编码电路包括EXZ检测单元，NRZ脉冲发生单元和输出控制单元。 EXZ检测单元接收指示NRZ信号的串行数据和指示码规则的二进制信息，并输出EXZ脉冲和延迟数据。 NRZ脉冲发生单元从EXZ检测单元接收EXZ脉冲，并输出EXZ检测信号，双极规则脉冲和违反脉冲。输出控制单元从EXZ检测单元接收EXZ检测信号，双极规则脉冲和违规脉冲，从NRZ脉冲发生单元输出延迟数据，并输出P极脉冲和N极脉冲到外部级，并且向NRZ脉冲产生单元发送奇数信号。

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