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1. 发明授权

US5764075A Input circuit for mode setting 失效
标题翻译：模式设定输入电路
公开(公告)号：US5764075A
公开(公告)日：1998-06-09
申请号：US736498
申请日：1996-10-24
申请人： Kiyoshi Fukushima
发明人： Kiyoshi Fukushima
IPC分类号： G06F1/32 , G06F15/78 , H03K19/00 , H03K19/003 , H03K17/173
CPC分类号： H03K19/003 , H03K19/0016
摘要： In order to provide an input circuit for mode setting with a simple configuration sufficiently stable and without unnecessary current consumption, the input circuit of the invention, for outputting a control signal (MODE OUT) according to a status of a mode setting terminal (I1), comprises latch means (100) being reset with a rising edge of a reset signal (RES) to output the control signal (MODE OUT) of logic LOW and latching logic of the mode setting terminal (I1) with a falling edge of a delayed signal (RESD) of said reset signal (RES) for maintaining to output inverse or the same logic of said logic of the mode setting terminal (I1) latched, and pull-up or pull-down means (P1) becoming ON for pulling up or down the mode setting terminal (I1) to logic HIGH or LOW when the mode setting terminal (I1) is left open gated by logic LOW of the control signal (MODE OUT) and becoming OFF for cutting a current flowing through the mode setting terminal (I1) gated by logic HIGH of the control signal (MODE OUT).
摘要翻译：为了提供具有足够稳定且没有不必要的电流消耗的简单配置的模式设置的输入电路，本发明的输入电路用于根据模式设置端子（I1）的状态输出控制信号（MODE OUT）包括以复位信号（RES）的上升沿复位的锁存装置（100），以输出逻辑低电平的控制信号（MODE OUT）和模式设置端子（I1）的锁存逻辑，其延迟的下降沿所述复位信号（RES）的信号（RESD）用于保持输出与锁存的模式设定端子（I1）的所述逻辑相反或相同的逻辑，并且上拉或下拉装置（P1）变为导通以拉起或者当模式设定端子（I1）由控制信号（MODE OUT）的逻辑低电位门开启时，模式设定端子（I1）变为逻辑高电平或低电平，并且变为OFF以切断流过模式设定端子的电流（I1）由逻辑高电平控制 gnal（MODE OUT）。

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