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1. 发明授权

US06552625B2 Processor with pulse width modulation generator with fault input prioritization 有权
公开(公告)号：US06552625B2
公开(公告)日：2003-04-22
申请号：US09870650
申请日：2001-06-01
申请人： Stephen A. Bowling
发明人： Stephen A. Bowling
IPC分类号： H03K0708
CPC分类号： H02P27/08 , G05B2219/34217
摘要： A processor that has pulse width modulation generation circuitry that provides an improved capability to deal with fault conditions, and particularly with multiple concurrent fault conditions, occurring in external circuitry and devices that are connected to PWM hardware included in a processor. A pulse width modulation generator for a processor includes fault priority circuitry having a plurality of fault inputs operable to receive fault input signals and a fault output operable to output a fault output signal, the fault priority circuitry operable to receive fault input signals on a plurality of fault inputs concurrently, and output a fault output signal corresponding to a fault input having a highest priority among the fault inputs that are receiving fault input signals, and pulse width modulation circuitry having at least one pulse width modulation output operable to output at least one pulse width modulated signal and a fault input operable to receive the fault output signal from the fault priority circuitry, the pulse width modulation circuitry operable to drive the pulse width modulation output to a defined state associated with the selected fault input.

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