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1. 发明授权

US06313537B1 Semiconductor device having multi-layered pad and a manufacturing method thereof 有权
标题翻译：具有多层焊盘的半导体装置及其制造方法
公开(公告)号：US06313537B1
公开(公告)日：2001-11-06
申请号：US09209315
申请日：1998-11-09
申请人： Sueng-Rok Lee , Myung-Sung Kim , Yunhee Lee , Manjun Kim
发明人： Sueng-Rok Lee , Myung-Sung Kim , Yunhee Lee , Manjun Kim
IPC分类号： H01L2398
CPC分类号： H01L24/05 , H01L24/03 , H01L2224/02166 , H01L2224/0401 , H01L2224/05093 , H01L2224/05095 , H01L2224/05096 , H01L2224/05556 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/04941 , H01L2924/14 , H01L2924/19041
摘要： Provided is a semiconductor device having a multi-layered pad, including a first interlevel insulating layer formed on a semiconductor substrate; a first conductive pad formed on the first interlevel insulating layer, the first conductive pad extending lengthwise along a first edge on a first side of a pad window region; a second interlevel insulating layer formed on the first interlevel insulating layer having a first via hole exposing a defined region of the first conductive pad; a first conductive plug formed in the first via hole; a second conductive pad formed on the second interlevel insulating layer, the second conductive pad extending lengthwise along the first edge on the first side of the pad window region and being electrically coupled to the first conductive plug; a third interlevel insulating layer formed on the second interlevel insulating layer having a second via hole exposing a defined region of the second conductive pad; a second conductive plug formed in the second via hole; and a third conductive pad formed on a defined region of the third interlevel insulating layer, the third conductive pad being electrically coupled to the second conductive plug. The semiconductor device further comprises a fourth interlevel insulating layer formed on the third interlevel insulating layer having a third via hole exposing a defined region of the third conductive pad and a fourth conductive pad formed on a defined region of the fourth interlevel insulating layer, the fourth conductive pad being electrically coupled to the third conductive pad. The semiconductor device even further comprises a plurality of buffer layers formed on at least one of the first and second interlevel insulating layers under the pad window region. The plurality of buffer layers is arranged either in a mosaic layout or in a zigzag manner.
摘要翻译：提供一种具有多层焊盘的半导体器件，包括形成在半导体衬底上的第一层间绝缘层; 形成在所述第一层间绝缘层上的第一导电焊盘，所述第一导电焊盘沿着垫窗区域的第一侧沿着第一边缘纵向延伸; 形成在所述第一层间绝缘层上的第二层间绝缘层具有暴露所述第一导电焊盘的限定区域的第一通孔; 形成在第一通孔中的第一导电插塞; 形成在所述第二层间绝缘层上的第二导电焊盘，所述第二导电焊盘沿着所述焊盘窗口区域的第一侧上的第一边缘纵向地延伸并且电耦合到所述第一导电插塞; 形成在所述第二层间绝缘层上的第三层间绝缘层具有暴露所述第二导电焊盘的限定区域的第二通孔; 形成在所述第二通孔中的第二导电插塞; 以及形成在所述第三层间绝缘层的限定区域上的第三导电焊盘，所述第三导电焊盘电耦合到所述第二导电插塞。所述半导体器件还包括形成在所述第三层间绝缘层上的第四层间绝缘层，具有暴露所述第三导电焊盘的限定区域的第三通孔和形成在所述第四层间绝缘层的限定区域上的第四导电焊盘，导电焊盘电耦合到第三导电焊盘。半导体器件甚至还包括形成在焊盘窗口区域下的第一和第二层间绝缘层中的至少一个上的多个缓冲层。多个缓冲层以马赛克布局或锯齿形布置。

2. 发明授权

US06316832B1 Moldless semiconductor device and photovoltaic device module making use of the same 失效
标题翻译：无模具半导体器件和光伏器件模块使用相同
公开(公告)号：US06316832B1
公开(公告)日：2001-11-13
申请号：US09190287
申请日：1998-11-13
申请人： Koji Tsuzuki , Tsutomu Murakami , Satoru Yamada , Yoshifumi Takeyama , Koichi Shimizu
发明人： Koji Tsuzuki , Tsutomu Murakami , Satoru Yamada , Yoshifumi Takeyama , Koichi Shimizu
IPC分类号： H01L2398
CPC分类号： H01L31/0504 , H01L23/051 , H01L23/3157 , H01L24/33 , H01L27/1421 , H01L31/0508 , H01L2224/83801 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01041 , H01L2924/01042 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01056 , H01L2924/01061 , H01L2924/01073 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/07802 , H01L2924/09701 , H01L2924/10253 , H01L2924/12032 , H01L2924/12042 , H01L2924/1301 , H01L2924/181 , H01L2924/207 , H01L2924/3011 , H02S20/23 , Y02B10/12 , Y02E10/50 , H01L2924/01046 , H01L2924/3512 , H01L2924/00 , H01L2224/48 , H01L2924/0002 , H01L2924/00012
摘要： A moldless semiconductor device comprising a semiconductor chip held between outer-connecting terminals and connected electrically to the terminals is provided. At least one of the two terminals has, at its region contiguous to the semiconductor chip or at its region contiguous to the semiconductor chip and a region vicinal thereto, a hardness different from all other regions of the one terminal. This moldless semiconductor device can withstand significant external force and exhibits high reliability when used in photovoltaic device modules.
摘要翻译：提供了一种无模制半导体器件，其包括保持在外部连接端子之间并与端子电连接的半导体芯片。两个端子中的至少一个在其与半导体芯片相邻的区域处或其邻近半导体芯片的区域和与其邻接的区域具有与一个端子的所有其它区域不同的硬度。该无模制半导体器件可以承受显着的外力，并且在光伏器件模块中使用时具有高可靠性。

3. 发明授权

US06204563B1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06204563B1
公开(公告)日：2001-03-20
申请号：US09192595
申请日：1998-11-17
申请人： Shinji Ohuchi , Noritaka Anzai , Yoshimi Egawa
发明人： Shinji Ohuchi , Noritaka Anzai , Yoshimi Egawa
IPC分类号： H01L2398
CPC分类号： H01L23/3121 , H01L23/293 , H01L2224/16 , H01L2924/15311
摘要： A semiconductor device for mounting on an external substrate includes a semiconductor chip, a high thermal elastic internal substrate and a high elastic liquid resin. The semiconductor chip has bump electrodes formed on its main surface. The high thermal elastic internal substrate includes a conductive pattern on one surface and external electrodes on the other surface. The conductive pattern is electrically connected to the bump electrodes. The external electrodes are electrically connected to the conductive pattern and mounted on the external substrate. The high elastic liquid resin covers the surface of the semiconductor chip, the one surface of the internal substrate and the bump electrodes. The internal substrate has a Young modulus of about 8000 to 15000 kg/mm2, which is larger than a Young modulus of the external substrate.
摘要翻译：用于安装在外部基板上的半导体器件包括半导体芯片，高热弹性内部基板和高弹性液体树脂。半导体芯片在其主表面上形成有凸起电极。高热弹性内部基板在一个表面上包括导电图案和另一个表面上的外部电极。导电图案电连接到凸块电极。外部电极电连接到导电图案并安装在外部基板上。高弹性液体树脂覆盖半导体芯片的表面，内部基板的一个表面和凸起电极。内部基材的杨氏模量为约8000〜15000kg / mm 2，大于外部基材的杨氏模量。

4. 发明授权

US06657314B2 Manipulation-proof integrated circuit 有权
公开(公告)号：US06657314B2
公开(公告)日：2003-12-02
申请号：US09963976
申请日：2001-09-26
申请人： Wolfgang Pockrandt
发明人： Wolfgang Pockrandt
IPC分类号： H01L2398
CPC分类号： H01L23/57 , G06F21/87 , H01L2924/0002 , H01L2924/00
摘要： The integrated circuit has a circuit with information that is protected by a covering shielding level. A network with a large number of nodes is formed in the shielding level. Some of the nodes are linked to a comparator for a nominal-actual comparison. The comparator checks for a characteristic output current from each node. Errors on the characteristic output current lead to a change in the information which is stored in the circuit, so that the latter is protected against manipulation or analysis.

5. 发明授权

US06680537B1 Semiconductor device having a dual damascene interconnect structure and method for manufacturing same 有权
标题翻译：具有双镶嵌互连结构的半导体器件及其制造方法
公开(公告)号：US06680537B1
公开(公告)日：2004-01-20
申请号：US09241461
申请日：1999-02-02
申请人： Koji Yamamoto
发明人： Koji Yamamoto
IPC分类号： H01L2398
CPC分类号： H01L21/76808 , H01L21/76807 , H01L2221/1031 , H01L2221/1036
摘要： A semiconductor device includes a first interlayer film of SiN and a second interlayer film of SiO2 that are formed in the order over a semiconductor substrate having, at a surface, a conductive layer. In the same or different etching process, a contact or via hole is formed through the first interlayer film above the conductive layer, while an interconnect trench is formed through the second interlayer film.
摘要翻译：半导体器件包括SiN的第一层间膜和SiO 2的第二层间膜，其在表面具有导电层的半导体衬底上依次形成。在相同或不同的蚀刻工艺中，通过导电层上方的第一层间膜形成接触或通孔，同时通过第二层间膜形成互连沟槽。

6. 发明授权

US06424042B1 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06424042B1
公开(公告)日：2002-07-23
申请号：US09505990
申请日：2000-02-17
申请人： Takeshi Kitani
发明人： Takeshi Kitani
IPC分类号： H01L2398
CPC分类号： H01L21/76816 , H01L21/76813 , H01L21/7684 , H01L23/522 , H01L24/03 , H01L24/05 , H01L2224/0401 , H01L2224/05546 , H01L2224/05556 , H01L2224/06517 , H01L2224/17517 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/04941 , H01L2924/05042
摘要： An interlayer film layer is formed on an (N−1)-th interconnection Layer via a barrier film, and an N-th interconnection layer is formed on the interlayer film layer. An interconnection having a Damascene structure is formed in the interconnection layer and the interlayer film layer. The interconnection has an wiring portion having a narrow line width and a pad portion having a wide line width. A recess corresponding to the wiring portion and the pad portion is provided in an insulating film of the interconnection layer. A recess corresponding to the pad portion is provided in an insulating film of the interlayer film layer. A barrier metal and a metal film are deposited in both the recesses, and unnecessary portions of the barrier metal and the metal film are removed by CMP, to form a multilayer interconnection structure.
摘要翻译：在第（N-1）布线层上经由阻挡膜形成层间膜层，在层间膜层上形成第N互连层。在互连层和层间膜层中形成具有镶嵌结构的互连。互连具有线宽窄的布线部分和线宽宽的焊盘部分。在互连层的绝缘膜中设置与布线部分和焊盘部分相对应的凹部。在该层间膜层的绝缘膜上设置与该焊盘部对应的凹部。在两个凹部中沉积阻挡金属和金属膜，通过CMP除去阻挡金属和金属膜的不必要部分，形成多层互连结构。

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