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1. 发明授权

US07706192B2 Voltage generating circuits for semiconductor memory devices and methods for the same 有权
标题翻译：用于半导体存储器件的电压产生电路及其方法
公开(公告)号：US07706192B2
公开(公告)日：2010-04-27
申请号：US12010465
申请日：2008-01-25
申请人： Young-Sun Min , Dong-Il Seo
发明人： Young-Sun Min , Dong-Il Seo
IPC分类号： G11C5/01
CPC分类号： G11C5/147 , G11C7/20 , G11C11/4072 , G11C11/4074
摘要： In a voltage generating circuit for a semiconductor memory device, each of a plurality of reset signal generators individually generates a reset signal in response to one of a plurality of external source voltages. The plurality of external source voltages have different voltage levels. An output voltage generator generates a plurality of output voltages by independently driving each of the plurality of external source voltages in response to a corresponding one of the plurality of reset signals. The output voltage generator outputs the plurality of output voltages through a common output terminal.
摘要翻译：在半导体存储器件的电压产生电路中，多个复位信号发生器中的每一个单独地响应于多个外部源极电压之一产生复位信号。多个外部源极电压具有不同的电压电平。输出电压发生器通过响应多个复位信号中的相应一个独立地驱动多个外部源电压中的每一个来产生多个输出电压。输出电压发生器通过公共输出端输出多个输出电压。

2. 发明授权

US07388800B2 Memory control device having less power consumption for backup 有权
标题翻译：内存控制设备具有较少的备用功耗
公开(公告)号：US07388800B2
公开(公告)日：2008-06-17
申请号：US11179539
申请日：2005-07-13
申请人： Tadaaki Maeda
发明人： Tadaaki Maeda
IPC分类号： G11C5/01
CPC分类号： G06F1/3275 , G06F1/30 , G06F1/3203 , G06F13/1668 , Y02D10/126 , Y02D10/13 , Y02D10/14
摘要： When it is detected that the voltage of a main power supply is reduced below a predetermined value during a normal operation, a power controller switches a power supply for a DRAM from the main power supply to a battery power supply and makes an instruction signal for instruction a self-refresh mode to a memory controller active. In response to this, the memory controller changes a clock enable signal for the DRAM to a low level to establish the self-refresh mode of the DRAM, and, after, the self-refresh mode of the DRAM is established, supplying of power to the memory controller is stopped. The clock enable signal for the DRAM is maintained to the low level by pull-down resistance even when the supplying of power to the memory controller is stopped from a condition that the signal is changed to the low level in the self-refresh mode, thereby maintaining the self-refresh mode of the DRAM.
摘要翻译：当在正常操作期间检测到主电源的电压被降低到低于预定值时，电源控制器将DRAM的电源从主电源切换到电池电源，并且产生用于指令的指令信号一个自刷新模式到一个内存控制器激活。响应于此，存储器控制器将用于DRAM的时钟使能信号改变为低电平以建立DRAM的自刷新模式，之后建立DRAM的自刷新模式，向内存控制器停止。即使当在自刷新模式中信号变为低电平的状态停止向存储器控制器供电时，DRAM的时钟使能信号也被下拉电阻维持在低电平，从而保持DRAM的自刷新模式。

3. 发明授权

US07697349B2 Word line boost circuit and method 有权
标题翻译：字线升压电路及方法
公开(公告)号：US07697349B2
公开(公告)日：2010-04-13
申请号：US11896177
申请日：2007-08-30
申请人： Yung-Feng Lin
发明人： Yung-Feng Lin
IPC分类号： G11C5/01
CPC分类号： G11C8/08 , G11C5/143 , G11C5/145 , H02M3/073
摘要： A word line boost circuit includes a first pump circuit, a first transistor, a voltage detection circuit and a second pump circuit. The first pump circuit provides a gate boosted signal according to an address transfer detection (ATD) signal. The first transistor has a control terminal for receiving the gate boosted signal and a second terminal coupled to a target word line. The voltage detection circuit is for detecting a voltage level of the gate boosted signal and accordingly outputting a detection signal. The second pump circuit is for outputting a boost signal to a first terminal of the first transistor according to a voltage level of the detection signal. The boost signal boosts the target word line via the turned-on first transistor.
摘要翻译：字线升压电路包括第一泵电路，第一晶体管，电压检测电路和第二泵电路。第一泵电路根据地址转移检测（ATD）信号提供门升压信号。第一晶体管具有用于接收栅极升压信号的控制端子和耦合到目标字线的第二端子。电压检测电路用于检测栅极升压信号的电压电平，从而输出检测信号。第二泵电路用于根据检测信号的电压电平将升压信号输出到第一晶体管的第一端。升压信号经由导通的第一晶体管升高目标字线。

4. 发明授权

US07483328B2 Voltage glitch detection circuits and methods thereof 有权
标题翻译：电压毛刺检测电路及其方法
公开(公告)号：US07483328B2
公开(公告)日：2009-01-27
申请号：US11434933
申请日：2006-05-17
申请人： Eui-Seung Kim , Jung-Hyun Kim
发明人： Eui-Seung Kim , Jung-Hyun Kim
IPC分类号： G11C5/01
CPC分类号： G11C7/1051 , G11C7/02 , G11C7/06 , G11C7/1063 , G11C29/026
摘要： Voltage glitch detection circuits and methods thereof. The voltage glitch detection circuit may include a monitoring memory array including at least one memory cell storing reference data, a monitoring sense amplifier receiving stored reference data from the monitoring memory array, amplifying the received stored reference data in response to an operation control signal and outputting data based on the reference data, a data storage circuit including at least one latch to store the reference data and a comparator circuit receiving and comparing the data output from the monitoring sense amplifier and the stored reference data from the data storage circuit, and outputting a detection signal based on the comparison. The voltage glitch detection circuit may include a first storage unit configured to latch a first voltage, a second storage unit configured to latch a second voltage, a first comparator circuit first comparing the latched first voltage with a first reference voltage and outputting a first comparison result, a second compariator circuit second comparing the second voltage with a second reference voltage and outputting a second comparison result and a third comparator circuit third comparing the first and second comparison results and outputting a reset detection signal based on the third comparison.
摘要翻译：电压毛刺检测电路及其方法。电压毛刺检测电路可以包括监视存储器阵列，其包括存储参考数据的至少一个存储器单元，监视读出放大器，接收来自监视存储器阵列的存储的参考数据，响应于操作控制信号放大所接收的存储的参考数据并输出基于参考数据的数据的数据存储电路，包括用于存储参考数据的至少一个锁存器的数据存储电路;以及比较器电路，接收和比较来自监视读出放大器的数据和来自数据存储电路的存储的参考数据，检测信号基于比较。电压毛刺检测电路可以包括被配置为锁存第一电压的第一存储单元，被配置为锁存第二电压的第二存储单元，第一比较器电路，首先将锁存的第一电压与第一参考电压进行比较，并输出第一比较结果第二比较器电路，其将所述第二电压与第二参考电压进行比较，并输出第二比较结果;以及第三比较器电路，其对所述第一和第二比较结果进行比较，并输出基于所述第三比较的复位检测信号。

5. 发明授权

US07430149B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07430149B2
公开(公告)日：2008-09-30
申请号：US11503941
申请日：2006-08-15
申请人： Kenji Yoshinaga , Fukashi Morishita
发明人： Kenji Yoshinaga , Fukashi Morishita
IPC分类号： G11C5/01
CPC分类号： G11C5/147
摘要： There is provided a semiconductor device supplied with internal power generated by an internal power generation circuit to perform a stable operation and, also, suppress power consumption. A control circuit, a row/column decoder and a sense amplifier are driven by an internal buck voltage. On the other hand, a data path with high power consumption is driven by an external power supply voltage. A level conversion circuit receives an address signal or a command signal having a voltage level of the external power supply voltage, converts the voltage level to the internal buck voltage, and outputs a resultant signal to the control circuit. A level conversion circuit receives a control signal having a voltage level of the internal buck voltage from the control circuit, converts the voltage level to the external power supply voltage, and outputs a resultant signal to the data path.
摘要翻译：提供了由内部发电电路产生的内部电力提供的半导体器件，以执行稳定的操作，并且还抑制功耗。控制电路，行/列解码器和读出放大器由内部降压电压驱动。另一方面，具有高功耗的数据路径由外部电源电压驱动。电平转换电路接收具有外部电源电压的电压电平的地址信号或指令信号，将电压电平转换为内部降压电压，并将结果信号输出到控制电路。电平转换电路从控制电路接收具有内部降压电压的电压电平的控制信号，将电压电平转换为外部电源电压，并将结果信号输出到数据通路。

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