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1. 发明授权

US06760795B2 Data queue system 失效
标题翻译：数据队列系统
公开(公告)号：US06760795B2
公开(公告)日：2004-07-06
申请号：US10035000
申请日：2001-12-28
申请人： Alistair Goudie , Colin Helliwell , Marcus Jones
发明人： Alistair Goudie , Colin Helliwell , Marcus Jones
IPC分类号： G06F306
CPC分类号： H04L49/901 , H04L49/90 , H04L69/22
摘要： A data queue system comprises plural memory blocks defined in memory, and a queue which comprises a number of memory blocks each including a link to the following block in the data queue. A queue descriptor includes identities which identify: the final block in the queue, the memory location where the most recent read commit occurred (and optionally an offset from a predetermined location in that block), the memory location where the most recent write commit occurred (and optionally an offset from a predetermined location in that memory block), the size of the blocks, the memory location the most recent write occurred, the number of unused blocks, the number of blocks which contain data to be read, the type of data queue, the memory location where the most recent read occurred and the number of blocks which have been read since the most recent read commit.
摘要翻译：数据队列系统包括在存储器中定义的多个存储器块，以及包括多个存储器块的队列，每个存储块包括到数据队列中的后续块的链接。队列描述符包括标识的身份：队列中的最后块，发生最近的读提交的存储器位置（以及可选地，该块中的预定位置的偏移），发生最近的写提交的存储器位置（并且可选地从该存储器块中的预定位置的偏移），块的大小，最近写入的存储器位置，未使用块的数量，包含要读取的数据的块的数量，数据的类型队列，发生最新读取的存储器位置以及自最近读取提交以来已读取的块数。

2. 发明授权

US06615294B1 Recording/reproducing apparatus using an IC memory 失效
标题翻译：使用IC存储器的记录/再现装置
公开(公告)号：US06615294B1
公开(公告)日：2003-09-02
申请号：US09182792
申请日：1998-10-30
申请人： Kiyotaka Yamanoi
发明人： Kiyotaka Yamanoi
IPC分类号： G06F306
CPC分类号： G11B20/10527 , G11B2020/10666 , G11B2020/10675 , G11B2220/61 , G11C7/16 , G11C2207/16
摘要： A recording/reproducing apparatus using an IC memory includes an IC memory to/from which writing/reading of an audio signal is performed; and a control circuit for controlling writing/reading of the audio signal to/from this IC memory, and its address, and for controlling, on writing and reading the audio signal to and from the IC memory, so that its address becomes ring-shaped, writing, of when a recording key is pressed, the audio signal from contiguous address to an area, within the IC memory where the writing, which has never been read is performed, and reading, of when a reproduction key is pressed, the audio signal from the head of an area within the IC memory where the writing, which has never been read, is performed.
摘要翻译：使用IC存储器的记录/再现装置包括执行音频信号的写/读的IC存储器; 以及控制电路，用于控制对该IC存储器的音频信号的写入/读取及其地址，并且用于在向IC存储器写入和读取音频信号之后控制其地址变为环形当记录键被按下时，来自连续地址的音频信号到执行了从未被读取的写入的IC存储器内的区域，以及当按下再现键时读取音频来自IC存储器内的从未被读取的写入的区域的头部的信号被执行。

3. 发明授权

US06487616B1 Controller for data recorder 有权
标题翻译：数据记录器控制器
公开(公告)号：US06487616B1
公开(公告)日：2002-11-26
申请号：US09718173
申请日：2000-11-21
申请人： Koji Hayashi
发明人： Koji Hayashi
IPC分类号： G06F306
CPC分类号： G06F3/0619 , G06F3/0656 , G06F3/0677 , G11B7/0045 , G11B7/005 , G11B19/04 , G11B20/10009 , G11B20/10527 , G11B20/1217 , G11B27/10 , G11B27/11 , G11B27/19 , G11B27/3027 , G11B27/3063 , G11B27/36 , G11B2020/10814 , G11B2220/216 , G11B2220/218 , G11B2220/2529 , G11B2220/2545 , G11B2220/65
摘要： A controller interrupts and restarts writing data from a buffer memory to a medium and prevents buffer underrun errors. The controller includes an address memory for storing a recording medium address or a buffer memory address, which indicate the location of the data when the interruption occurred. A synchronizing circuit sequentially reads data from the recording medium and data from the buffer memory prior to the interruption while synchronizing the written data and the stored data. A restart circuit restarts writing data when the recording medium address or the buffer memory address matches the address stored in the address memory.
摘要翻译：控制器中断并重新启动将数据从缓冲存储器写入介质，并防止缓冲区欠载错误。控制器包括用于存储记录介质地址或缓冲存储器地址的地址存储器，其指示当发生中断时数据的位置。同步电路在同步写入的数据和存储的数据的同时，在中断之前顺序地从记录介质读取数据和来自缓冲存储器的数据。当记录介质地址或缓冲存储器地址与存储在地址存储器中的地址匹配时，重启电路重新开始写入数据。

4. 发明授权

US06732061B1 Monitoring system and method implementing a channel plan 有权
标题翻译：实施渠道计划的监控系统和方法
公开(公告)号：US06732061B1
公开(公告)日：2004-05-04
申请号：US09451376
申请日：1999-11-30
申请人： James Wichelman , Bruce Votipka , Eric N. Flink , Craig Chamberlain
发明人： James Wichelman , Bruce Votipka , Eric N. Flink , Craig Chamberlain
IPC分类号： G06F306
CPC分类号： H04W52/34 , H04B17/327 , H04B17/391
摘要： A system includes a plurality of nodes. The plurality of nodes each communicate signals pursuant to a channel plan. The channel plan includes one or more predefined specifications for each of one or more signal channels on each of the plurality of nodes.
摘要翻译：系统包括多个节点。多个节点各自根据信道计划来传送信号。信道规划包括针对多个节点中的每一个上的一个或多个信号信道中的每一个的一个或多个预定义规范。

5. 发明授权

US06718435B2 Method and system for migrating data in a raid logical drive migration 有权
标题翻译：用于在RAID逻辑驱动器迁移中迁移数据的方法和系统
公开(公告)号：US06718435B2
公开(公告)日：2004-04-06
申请号：US09929445
申请日：2001-08-14
申请人： Linda Ann Riedle
发明人： Linda Ann Riedle
IPC分类号： G06F306
CPC分类号： G06F3/0601 , G06F11/1096 , G06F2003/0697 , G06F2211/1035
摘要： A method and system for improving data migration from source data stripes to destination stripes in a Redundant Array of Independent Drives (RAID) logical drive migration (LDM). The invention describes a procedure for checkpointing data migrations, so that if the system should fail in the middle of the LDM, the computer can resume the LDM from the last checkpointed destination stripes, thus ensuring accurate tracking of data location. Further, the invention also provides the capability of properly checkpointing a data write to a stripe according to whether or not the stripe unit has been migrated previously.
摘要翻译：一种用于改进在独立驱动器冗余阵列（RAID）逻辑驱动器迁移（LDM）中从源数据条带到目标条带的数据迁移的方法和系统。本发明描述了用于检查点数据迁移的过程，使得如果系统在LDM的中间失败，则计算机可以从最后检查点的目的地条带恢复LDM，从而确保数据位置的准确跟踪。此外，本发明还提供了根据条带单元是否已经被迁移来适当地检查对条带的数据写入的能力。

6. 发明授权

US06421747B1 Method for maximizing buffer usage on a disk drive 有权
标题翻译：最大化磁盘驱动器上缓冲区使用的方法
公开(公告)号：US06421747B1
公开(公告)日：2002-07-16
申请号：US09257391
申请日：1999-02-25
申请人： Aaron Wade Wilson
发明人： Aaron Wade Wilson
IPC分类号： G06F306
CPC分类号： G06F3/0613 , G06F3/0656 , G06F3/0674
摘要： A method for maximizing buffer usage in a disk drive system. Control circuitry within the disk drive system tansfers the defective sector list for the disk to a buffer, and places the list in a reserved list area. The size of the defective sector list is then determined and the reserved list area is reduced to a size equal to the size of the defective sector list plus some spare room. If the newly sized reserved list area is not at one end of the buffer, it is then moved to one end of the buffer to leave the remainder of the buffer as a contiguous and expanded reserved user area for use data. The expanded reserved user area reduces the time of read or write operations in a disk drive.
摘要翻译：一种用于最大化磁盘驱动器系统中的缓冲区使用的方法。磁盘驱动器系统中的控制电路将磁盘的缺陷扇区列表转换为缓冲区，并将列表放置在保留列表区域中。然后确定缺陷扇区列表的大小，并将保留列表区域减小到等于缺陷扇区列表的大小加上一些备用房间的大小。如果新大小的保留列表区域不在缓冲器的一端，则将其移动到缓冲器的一端，以将剩余的缓冲区留作连续和扩展的预留用户区域以供使用数据。扩展的预留用户区域减少了磁盘驱动器中读取或写入操作的时间。

7. 发明授权

US06324604B1 Magnetic disk storage for storing data in disk block size from fixed length of host block in non-integer multiple of the disk block size 失效
标题翻译：磁盘存储用于以非整数倍的磁盘块大小存储磁盘块大小固定长度的数据
公开(公告)号：US06324604B1
公开(公告)日：2001-11-27
申请号：US09111211
申请日：1998-07-07
申请人： Arieh Don , Erez Ofer , Natan Vishlitzky
发明人： Arieh Don , Erez Ofer , Natan Vishlitzky
IPC分类号： G06F306
CPC分类号： G06F3/0607 , G06F3/064 , G06F3/0661 , G06F3/0689 , G06F11/10 , G06F11/1004
摘要： A method and apparatus for enabling a magnetic disk storage device that stores data according to a first data structure characterized by a fixed-length disk block size to respond to input/output requests from a host that define data according to a different data structure characterized by a different fixed-length host block size. A host adapter transfers requests and data between the host and a cache memory in the magnetic disk storage device as host blocks. A disk adapter transfers requests and data between the cache memory and magnetic disks as disk blocks. CRC data and a sector number are appended to each host block in a set of disk blocks.
摘要翻译：一种用于使磁盘存储装置能够存储数据的磁盘存储装置，该磁盘存储装置根据以固定长度的磁盘块大小为特征的第一数据结构来响应来自主机的输入/输出请求，该主机根据不同的数据结构定义数据，不同的固定长度的主机块大小。主机适配器将主机与磁盘存储设备中的高速缓冲存储器之间的请求和数据作为主机传输。磁盘适配器将缓存和磁盘之间的请求和数据作为磁盘块传输。 CRC数据和扇区号附加到一组磁盘块中的每个主机块。

8. 发明授权

US06772285B2 System and method for identifying busy disk storage units 有权
标题翻译：用于识别繁忙磁盘存储单元的系统和方法
公开(公告)号：US06772285B2
公开(公告)日：2004-08-03
申请号：US09726498
申请日：2000-11-30
申请人： Arkadi L. Litvin
发明人： Arkadi L. Litvin
IPC分类号： G06F306
CPC分类号： G06F3/0611 , G06F3/0647 , G06F3/0653 , G06F3/0683 , G06F11/3409 , G06F11/3452 , G06F11/3485 , G06F2201/81 , G06F2201/87
摘要： A busy disk evaluation system includes a busy disk evaluation module and a control module. The busy disk evaluation module is configured to perform a busy disk evaluation operation in which it processes access request statistics relating to access requests directed to a server, the server including a plurality of disk storage units, respective access requests requesting access to respective ones of the disk storage units, to identify which, if any of the disk storage units is busy. The busy disk evaluation module is configured to determine whether a disk storage unit is busy in relation to a ratio between the number of access requests requesting access to the disk storage unit per unit time exceeds a selected access request per unit time threshold in relation to a total number of access requests and a selected ratio threshold. The control module is configured to control the busy disk evaluation module. In that operation, the control module is configured to provide the busy disk evaluation module with the selected ratio threshold.
摘要翻译：繁忙的磁盘评估系统包括一个繁忙的磁盘评估模块和一个控制模块。繁忙磁盘评估模块被配置为执行繁忙磁盘评估操作，其中它处理与针对服务器的访问请求相关的访问请求统计，所述服务器包括多个磁盘存储单元，请求访问相应的访问请求磁盘存储单元，以确定哪个磁盘存储单元正忙。繁忙磁盘评估模块被配置为确定磁盘存储单元是否正在忙于与每单位时间请求访问磁盘存储单元的访问请求的数量之间的比率超过相对于单位时间阈值的所选访问请求访问请求的总数和所选的比例阈值。控制模块配置为控制繁忙磁盘评估模块。在该操作中，控制模块被配置为向忙盘评估模块提供所选择的比率阈值。

9. 发明授权

US06662248B2 Recording/reproducing apparatus using an IC memory 失效
公开(公告)号：US06662248B2
公开(公告)日：2003-12-09
申请号：US10047082
申请日：2002-01-15
申请人： Kiyotaka Yamanoi
发明人： Kiyotaka Yamanoi
IPC分类号： G06F306
CPC分类号： G11B20/10527 , G11B2020/10666 , G11B2020/10675 , G11B2220/61 , G11C7/16 , G11C2207/16
摘要： A recording/reproducing apparatus using an IC memory, comprising: an IC memory to/from which writing/reading of an audio signal is performed; and a control circuit for controlling writing/reading of the audio signal to/from this IC memory, and its address, and controlling, on writing and reading the audio signal to and from the IC memory, so that its address becomes ring-shaped, writing, when a recording key is pressed, the audio signal from an address contiguous to an area, within the IC memory, where the writing, which has never been read after the writing, is performed, and reading, when a reproduction key is pressed, the audio signal from the head of an area, within the IC memory, where the writing, which has never been read after the writing, is performed.

10. 发明授权

US06363441B1 TIMING CONTROLLER HAVING DEPENDENCY MEMORY, SELECTION SERIALIZATION COMPONENT AND REORDERING COMPONENT FOR MAINTAINING TIME DEPENDENCIES IN CONVERSIONS BETWEEN SEQUENTIAL AND PARALLEL OPERATIONS USING STAGING MEMORY 有权
标题翻译：具有相关性存储器的时序控制器，选择序列化组件和后台组件，用于使用分层存储器维持顺序和并行操作之间的转换中的时间依赖
公开(公告)号：US06363441B1
公开(公告)日：2002-03-26
申请号：US09263185
申请日：1999-03-05
申请人： Ole Bentz , Ian O'Donnell
发明人： Ole Bentz , Ian O'Donnell
IPC分类号： G06F306
CPC分类号： G06T15/04
摘要： An electronic system and method that maintains time dependencies and ordering constraints in an electronic system. A timing controller utilizes a representative bit to track timing dependencies associated with information and ensures the information is communicated and processed in an order that preserves the timing dependencies as the information is converted from parallel to parallel or parallel to serial operations. The present invention tracks the order in which information is loaded in a electronic hardware component and ensures that the information loaded into the electronic hardware component at a particular time is processed without interruption by information loaded at a different time. For example, the timing controller tracks the order in which texel information associated with a pixels parallelly loaded in a staging memory and issues electronic signals that cause the information loaded at a particular time to sequentially empty without interruption by information parallelly loaded in the staging memory at a different time.
摘要翻译：一种在电子系统中保持时间依赖性和排序限制的电子系统和方法。定时控制器利用代表性的比特来跟踪与信息相关联的定时依赖性，并确保信息被传送和处理，以便当信息从并行转换为并行或并行到串行操作时，保持时序依赖性。本发明追踪在电子硬件组件中加载信息的顺序，并且确保在特定时间加载到电子硬件组件中的信息被处理，而不会因不同时间加载的信息而中断。例如，定时控制器跟踪与平行加载在分段存储器中的像素相关联的纹理信息的顺序，并且发出电子信号，其导致在特定时间加载的信息不间断地通过并行加载在分段存储器中的信息中断不同的时间

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