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1. 发明授权

US12041856B2 Superconducting circuit provided on an encapsulated vacuum cavity 有权
公开(公告)号：US12041856B2
公开(公告)日：2024-07-16
申请号：US17037191
申请日：2020-09-29
申请人： International Business Machines Corporation
发明人： Isaac Lauer , Karthik Balakrishnan , Jeffrey Sleight , David James Frank
IPC分类号： H01L23/02 , H10N60/01 , H10N60/81 , H10N60/83 , H10N69/00 , H01L21/56
CPC分类号： H10N60/01 , H10N60/81 , H10N60/83 , H10N69/00 , H01L21/56
摘要： Devices, systems, methods, and/or computer-implemented methods that can facilitate a qubit device comprising a superconducting circuit provided on an encapsulated vacuum cavity are provided. According to an embodiment, a device can comprise a substrate having an encapsulated vacuum cavity provided on the substrate. The device can further comprise a superconducting circuit provided on the encapsulated vacuum cavity.

2. 发明公开

US20240127098A1 COMPACT SILICON QUBIT CELL WITH EMBEDDED READOUT 审中-公开
公开(公告)号：US20240127098A1
公开(公告)日：2024-04-18
申请号：US18275998
申请日：2022-03-04
申请人： Quantum Motion Technologies Limited
发明人： Miguel Fernando Gonzalez-Zalba
IPC分类号： G06N10/40 , G01R21/00 , H01P7/08 , H03K17/92 , H10N60/01 , H10N60/10
CPC分类号： G06N10/40 , G01R21/00 , H01P7/08 , H03K17/92 , H10N60/01 , H10N60/11 , H10N60/128
摘要： A quantum device is disclosed having an LC resonator circuit for performing qubit measurement or readout. The device comprises a silicon layer (601), a dielectric layer (603) disposed upon and forming a functional interface with the silicon layer (601), a first metallic region (614) disposed upon the dielectric layer 603, and a second metallic region (624) disposed upon the dielectric layer 603 and laterally separated from the first metallic region (614). The first and second metallic regions (614, 624) are arranged to be electrically connected such that a double quantum dot, forming a qubit having a first state and a second state, can be induced beneath the first and second metallic regions (614, 624) at the functional interface. The double quantum dot provides a capacitor C1 in the LC resonator circuit and the capacitance of the double quantum dot is dependent on the state of the qubit. The first metallic region (614) provides an inductor L1 in the LC resonator circuit, and the resonant frequency of the LC resonator circuit is dependent on the state of the qubit such that the state of the qubit can be measured or inferred.

3. 发明授权

US11930721B2 Systems and methods for fabrication of superconducting integrated circuits 有权
公开(公告)号：US11930721B2
公开(公告)日：2024-03-12
申请号：US16870537
申请日：2020-05-08
申请人： D-WAVE SYSTEMS INC.
发明人： Eric Ladizinsky , Jeremy P. Hilton , Byong Hyop Oh , Paul I. Bunyk
IPC分类号： H10N60/01 , B82Y10/00 , H01L21/285 , H01L21/768 , H10N60/10 , H10N60/12 , H10N60/80 , H10N60/85 , H10N69/00 , G06N10/00
CPC分类号： H10N60/0912 , B82Y10/00 , H01L21/2855 , H01L21/76877 , H01L21/76891 , H10N60/01 , H10N60/0156 , H10N60/10 , H10N60/12 , H10N60/805 , H10N60/855 , H10N69/00 , G06N10/00
摘要： Various techniques and apparatus permit fabrication of superconductive circuits. A niobium/aluminum oxide/niobium trilayer may be formed and individual Josephson Junctions (JJs) formed. A protective cap may protect a JJ during fabrication. A hybrid dielectric may be formed. A superconductive integrated circuit may be formed using a subtractive patterning and/or additive patterning. A superconducting metal layer may be deposited by electroplating and/or polished by chemical-mechanical planarization. The thickness of an inner layer dielectric may be controlled by a deposition process. A substrate may include a base of silicon and top layer including aluminum oxide. Depositing of superconducting metal layer may be stopped or paused to allow cooling before completion. Multiple layers may be aligned by patterning an alignment marker in a superconducting metal layer.

4. 发明授权

US11917927B2 Qubit assembly, qubit assembly preparation method, chip, and device 有权
公开(公告)号：US11917927B2
公开(公告)日：2024-02-27
申请号：US17972434
申请日：2022-10-24
申请人： Tencent Technology (Shenzhen) Company Limited
发明人： Chenji Zou , Yarui Zheng , Hui Wang
IPC分类号： H10N60/01 , H10N60/81
CPC分类号： H10N60/01 , H10N60/815
摘要： A production line device prepares a superconducting circuit layer on a substrate. The device prepares an under bump metallization (UBM) layer on an upper surface of the superconducting circuit layer. A superconducting connection is formed between the UBM layer and the superconducting circuit layer. The production device prepares a welding spot on an upper surface of the UBM layer to obtain a qubit assembly configured for a flip-chip superconducting quantum chip. A superconducting electrical connection is formed between the welding spot and the UBM layer.

5. 发明授权

US11871682B2 Quantum device and method of manufacturing the same 有权
公开(公告)号：US11871682B2
公开(公告)日：2024-01-09
申请号：US17349180
申请日：2021-06-16
申请人： NEC Corporation
发明人： Kenji Nanba , Ayami Yamaguchi , Akira Miyata , Katsumi Kikuchi , Suguru Watanabe , Takanori Nishi , Hideyuki Satou
IPC分类号： H10N60/81 , H01L23/498 , H01L23/34 , H10N60/01 , G06N10/00
CPC分类号： H10N60/81 , H01L23/34 , H01L23/49822 , H01L23/49838 , H10N60/01 , G06N10/00 , H01L23/49827 , H01L23/49888
摘要： A quantum device (100) includes: an interposer (112); a quantum chip (111); a first connection part (130) that is provided between the interposer (112) and the quantum chip (111) and electrically connects a wiring layer of the interposer (112) to a wiring layer of the quantum chip (111); and a second connection part (140) that is provided on a main surface of the interposer (112) where the first connection part (130) is arranged and is connected to a cooling plate (115).

6. 发明公开

US20230276718A1 METHOD OF FABRICATING A SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20230276718A1
公开(公告)日：2023-08-31
申请号：US18016118
申请日：2020-07-16
申请人： Microsoft Technology Licensing LLC
发明人： Amrita Singh , Elvedin Memisevic , Peter Krogstrup Jeppesen
IPC分类号： H10N60/80 , H01L29/06 , G06N10/00 , H10N60/01
CPC分类号： H10N60/80 , H01L29/0676 , G06N10/00 , H10N60/01
摘要： A semiconductor device is fabricated by: forming a shadow wall on a substrate; subsequently growing a nanowire of semiconductor material on the substrate; and directionally depositing a layer of a further material on the nanowire from a direction selected such that the shadow wall casts a shadow on the nanowire, the shadow being a region in which the further material is not deposited. The nanowire is vertically orientated relative to the substrate. The shadow wall comprises a base portion and a bridge portion. The bridge portion overhangs the substrate and is supported by the base portion. Patterning of the further material may be achieved without the use of etching, thereby avoiding damage to the semiconductor. Also provided is a semiconductor-superconductor hybrid device; a quantum computing device comprising the semiconductor-superconductor hybrid device; and a shadow wall for controlling directional deposition of a material.

7. 发明授权

US11707000B2 Side-gating in selective-area-grown topological qubits 有权
公开(公告)号：US11707000B2
公开(公告)日：2023-07-18
申请号：US16756437
申请日：2018-06-27
申请人： Microsoft Technology Licensing, LLC
发明人： Dmitry Pikulin , Michael H. Freedman , Roman Lutchyn , Peter Krogstrup Jeppesen , Parsa Bonderson
IPC分类号： H10N60/01 , G06N10/00 , H10N60/84 , H10N60/10
CPC分类号： H10N60/01 , G06N10/00 , H10N60/128 , H10N60/84
摘要： A quantum device is fabricated by forming a network of nanowires oriented in a plane of a substrate to produce a Majorana-based topological qubit. The nanowires are formed from combinations of selective-area-grown semiconductor material along with regions of a superconducting material. The selective-area-grown semiconductor material is grown by etching trenches to define the nanowires and depositing the semiconductor material in the trenches. A side gate is formed in an etched trench and situated to control a topological segment of the qubit.

8. 发明公开

US20230217841A1 Diode Devices Based on Superconductivity 审中-公开
公开(公告)号：US20230217841A1
公开(公告)日：2023-07-06
申请号：US17986774
申请日：2022-11-14
申请人： PsiQuantum Corp.
发明人： Faraz Najafi , Syrus Ziai
IPC分类号： H10N60/83 , H01L29/861 , B32B17/10 , B32B37/26 , H01L21/683 , H01L23/24 , H01L27/12 , H10N60/01 , H10N60/20 , H10N60/30 , H10N60/82
CPC分类号： H10N60/83 , H01L29/861 , B32B17/1055 , B32B37/26 , H01L21/6835 , H01L23/24 , H01L27/1266 , H10N60/01 , H10N60/20 , H10N60/30 , H10N60/82 , H01L2221/6835 , H01L2221/68395
摘要： An electronic device (e.g., a diode) is provided that includes a substrate and a patterned layer of superconducting material disposed over the substrate. The patterned layer forms a first electrode, a second electrode, and a loop coupling the first electrode with the second electrode by a first channel and a second channel. The first channel and the second channel have different minimum widths. For a range of current magnitudes, when a magnetic field is applied to the patterned layer of superconducting material, the conductance from the first electrode to the second electrode is greater than the conductance from the second electrode to the first electrode.

9. 发明公开

US20230217840A1 SILICON QUANTUM DEVICE STRUCTURES DEFINED BY METALLIC STRUCTURES 审中-公开
公开(公告)号：US20230217840A1
公开(公告)日：2023-07-06
申请号：US18008896
申请日：2021-08-05
申请人： Quantum Motion Technologies Limited
发明人： Sofia Patomaki , John Morton
IPC分类号： H10N60/10 , H10N60/01 , H03K17/92
CPC分类号： H10N60/128 , H10N60/11 , H10N60/01 , H03K17/92
摘要： A silicon-based quantum device is provided. The device comprises: a first metallic structure (501); a second metallic structure (502) laterally separated from the first metallic structure; and an L-shaped elongate channel (520) defined by the separation between the first and second metallic structures; wherein the elongate channel has a vertex (505) connecting two elongate parts of the elongate channel. The device further comprises: a third metallic structure (518), mediator gate, positioned in the elongate channel; a fourth metallic structure (531) forming a first barrier gate, arranged at a first end of the third metallic structure; and a fifth metallic structure (532) forming a second barrier gate arranged at a second end of the third metallic structure. The first, second, third, fourth and fifth metallic structures are configured for connection to first, second, third, fourth and fifth electric potentials respectively. The first, second, fourth and fifth electric potentials are controllable to define an electrical potential well to confine quantum charge carriers in an elongate quantum dot beneath the elongate channel. The fourth and fifth electric potentials and the position of the fourth and fifth metallic structures define first and second ends of the elongate channel respectively. The width of the electrical potential well is defined by the position of the first and second metallic structures and their corresponding electric potentials; and the length of the electrical potential well is defined by the position of the fourth and fifth metallic structures and their corresponding electric potentials. The third electric potential is controllable to adjust quantum charge carrier energy levels in the electrical potential well.

10. 发明公开

US20240284807A1 A SAMPLE HOLDER AND A METHOD OF OPERATING IT 审中-公开
公开(公告)号：US20240284807A1
公开(公告)日：2024-08-22
申请号：US18573683
申请日：2022-05-23
申请人： QDEVIL APS
发明人： Soren ANDRESEN , Peter Ulrik KANN , Merlin VON SOOSTEN
IPC分类号： H10N60/81 , H10N60/01
CPC分类号： H10N60/81 , H10N60/01
摘要： A sample holder for a quantum device, the sample holder comprising a first portion comprising a first cavity, a second portion comprising a second cavity, first fixing elements comprising a printed circuit board comprising one or more electrical conductor(s) and/or wave guide(s), and second fixing elements configured to fix the first and second portions to each other, wherein the quantum device is provided over and covering at least part of the first cavity, the quantum device is provided over and covering at least part of the second cavity, the quantum device is fixed to the first portion by the first fixing elements and the electrical conductor(s) and/or wave guide(s) is/are connected to the quantum device and extend to outside of the first and second portions.

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