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    • 3. 发明授权
    • Method and apparatus for generating a noiseless sliding block code for a
(2,7) channel with rate 1/2
    • 用于产生速率为1/2的(2,7)通道的无噪声滑块代码的方法和装置
    • US4463344A
    • 1984-07-31
    • US336478
    • 1981-12-31
    • Roy L. AdlerMartin Hassner
    • Roy L. AdlerMartin Hassner
    • H03M5/04G06F5/00G06T9/00G11B20/14H03M7/14H03M7/40H03K13/24
    • H03M7/4025G06T9/005G11B20/1426
    • An algorithm and the hardware embodiment for producing a run length limited code useful in magnetic recording channels are described. The system described produces sequences which have a minimum of 2 zeros and a maximum of 7 zeros between adjacent 1's. The code is generated by a sequential scheme that maps 1 bit of unconstrained into 2 bits of constrained data. The encoder is a finite state machine whose internal state description requires 3 bits. It possesses the attractive feature of reset data blocks which reset it to a fixed state. The decoder requires a lookahead of three future channel symbols (6 bits) and its operation is channel state independent. The error propagation due to a random error is 3 bits. The hardware implementation is extremely simple and can operate at very high data speeds.
    • 描述用于产生在磁记录通道中有用的游程长度有限代码的算法和硬件实施例。 所描述的系统产生具有最少2个零和相邻1之间最多7个零的序列。 代码由将1位无约束映射为2位受限数据的顺序方案生成。 编码器是一个有限状态机,其内部状态描述需要3位。 它具有复位数据块的有吸引力的特征,将其重置为固定状态。 解码器需要对未来三个通道符号(6位)进行前瞻,其操作是通道状态独立的。 由于随机误差引起的误差传播是3位。 硬件实现非常简单,可以在非常高的数据速度下运行。
    • 4. 发明授权
    • Variable block length synchronization system
    • 可变块长度同步系统
    • US3873920A
    • 1975-03-25
    • US42663173
    • 1973-12-12
    • BELL TELEPHONE LABOR INC
    • APPLE JR GARRETT GORDONCHING YAU CHAU
    • H03M7/40H04L7/04G08C25/00
    • H03M7/4025H04L7/043H04L7/048
    • Framing or block synchronization of digital information signals grouped in blocks of variable length is provided by preceding each block with a synchronization code word. Each synchronization code word is error correction encoded in accordance with a BCH code to indicate the number of information bits in the following block and, hence, the location of the next succeeding synchronization code word. Since only the synchronization code words are error correction encoded, they can be distinguished from the information bits to obtain synchronization. A synchronization receiver acquires synchronization upon the occurrence of an error-free synchronization code word in the incoming signal. Synchronization is maintained thereafter by utilizing the inherent error correction capability offered by the BCH code to correct up to two errors in each received synchronization code word before decoding it to locate the next synchronization word. If, however, three errors are detected in a received synchronization word, synchronization is assumed to be lost and synchronization is thereafter recovered with the occurrence of a succeeding error-free synchronization code word in the incoming digital signal. Two receiver embodiments are disclosed which perform the above-described operation. The first embodiment is adapted to perform a general type of framing synchronization, while the other embodiment is specifically adapted to provide video synchronization.
    • 由前面的每个块提供具有可变长度的块的数字信息信号的成帧或块同步,具有同步码字。 每个同步码字根据BCH码进行纠错编码,以指示随后块中的信息比特数,并因此指示下一个后续同步码字的位置。 由于仅对同步码字进行纠错编码,所以可以将其与信息比特进行区分以获得同步。 同步接收器在进入信号中发生无差错同步码字时获得同步。 此后,通过利用由BCH码提供的固有的纠错能力,在解码之前对每个接收到的同步码字中的两个错误进行校正以定位下一个同步字,从而维持同步。 然而,如果在接收的同步字中检测到三个错误,则假设同步被丢失,然后在输入数字信号中出现随后的无错误同步码字的同时被恢复。 公开了执行上述操作的两个接收机实施例。 第一实施例适于执行一般类型的成帧同步,而另一实施例特别适于提供视频同步。
    • 5. 发明授权
    • Method and apparatus of error detection for variable length words using a polynomial code
    • 使用多项式代码对可变长度字进行错误检测的方法和装置
    • US3872430A
    • 1975-03-18
    • US41835173
    • 1973-11-23
    • BOUDREAU PAUL EMILEBRODD WAYNE DONALDDONNAN ROBERT ANDERSON
    • BOUDREAU PAUL EMILEBRODD WAYNE DONALDDONNAN ROBERT ANDERSON
    • H03M13/00G06F11/10H03M7/40H03M13/03H04L1/00G06F11/12
    • H04L1/0057H03M7/4025H03M13/03
    • In the transmission of variable length frames of digital information separated by one or more flag sequences, a block check is generated and appended to the information bits at the transmitter. The block check is generated by Exclusive OR''ing a predetermined non-zero number to the high order information bits and generating (n-k) check digits according to a cyclic error detecting code. The (n-k) check digits are Exclusive OR''d with an (n-k) bit non-zero number to produce the block check. At the receiver, the first mentioned non-zero number is added to the high order information bits and an (n-k) digit number is generated according to the same cyclic error detecting code used at the transmitter. This number is checked to see if it conforms to a predetermined number indicating error-free transmission. Utilizing the above approach, transmission errors in or near the flag sequence are detected, as well as those which may occur in the information field.
    • 在由一个或多个标志序列分隔的数字信息的可变长度帧的传输中,生成块检查并将其附加到发射机的信息位。 通过根据循环错误检测码将高位信息比特和预定的非零号异或并产生(n-k)个校验位来产生块检查。 (n-k)个校验位是与(n-k)位非零数字异或运算以产生块检查。 在接收机中,将第一个提到的非零数加到高位信息位,并且根据在发射机使用的相同的循环检错码生成(n-k)位数。 检查该号码是否符合指示无错传输的预定数字。 利用上述方法,检测标志序列中或附近的传输错误以及可能在信息字段中发生的错误。
    • 6. 发明授权
    • Processing of compacted data
    • 压缩数据的处理
    • US3717851A
    • 1973-02-20
    • US3717851D
    • 1971-03-03
    • IBM
    • COCKE JMOMMENS JRAVIV J
    • H03M7/40H03M7/42G06F5/02G06F7/34
    • H03M7/425H03M7/4025
    • This data processing technique utilizes compacted data in the form of variable-length codes having length-representing prefix portions which themselves are variable-length encoded. The relatively small amount of storage needed when such a code format is used enables data to be conveniently encoded and handled as groups of characters rather than as single characters. The variable-length prefixes are decoded by a small, fast, searchonly type of associative memory which furnishes a matchindicating signal as an address to another memory having conventional storage elements. The output of the latter may contain a base address in still another memory of conventional type and an indication of how many bits remain in the current variable-length code word. These remaining bits furnish a displacement value which, in combination with the base address, will locate the decoded fixed-length word or character group in the last memory unit. In those instances where the length of the variable-length codes would become excessively long (for the less frequently occurring character groups) the original fixed-length codes are employed, each being preceded by a common ''''COPY'''' code. A special decoding procedure is invoked by this copy code.
    • 该数据处理技术利用具有长度代表前缀部分的可变长度代码形式的压缩数据,其长度代表前缀部分本身是可变长度编码的。 当使用这种代码格式时所需的相对较少量的存储使数据能够被方便地编码并且以字符组而不是单个字符来处理。 可变长度前缀由小型,快速的仅搜索类型的关联存储器解码,其将匹配指示信号作为地址提供给具有常规存储元件的另一存储器。 后者的输出可以在常规类型的另一个存储器中包含基地址,以及当前可变长度代码字中剩余多少位的指示。 这些剩余的位提供位移值,该位移值与基地址组合将在最后一个存储单元中定位解码的固定长度字或字符组。 在可变长度代码的长度变得过长(对于较不频繁出现的字符组)的情况下,采用原始固定长度代码,每个代码前面都有一个常用的“COPY”代码。 此复制代码调用特殊的解码过程。