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1. 发明申请

US20150280734A1 Sigma-Delta Analog-to-Digital Converter 有权
标题翻译： Sigma-Delta模数转换器
公开(公告)号：US20150280734A1
公开(公告)日：2015-10-01
申请号：US14659639
申请日：2015-03-17
申请人： MONTAGE TECHNOLOGY (SHANGHAI) CO., LTD.
发明人： Xiaomin Si
IPC分类号： H03M3/00
CPC分类号： H03M3/464 , H03M1/00 , H03M1/12 , H03M3/30 , H03M3/322 , H03M3/424 , H03M3/454 , H03M3/478 , H04L25/03038
摘要： The application disclose a sigma-delta analog-to-digital converter. The converter comprises: a summing stage, configured to receive an input signal and subtract a first feedback signal and a second feedback signal from the input signal to generate a difference signal; a loop filter coupled to an output node of the summing stage, and configured to filter the difference signal; a quantizer coupled to an output node of the loop filter, and configured to quantize the filtered difference signal to generate a quantized signal, and to generate an overload signal according to the filtered difference signal, wherein the overload signal indicates whether the filtered difference signal is overloaded and/or an overload amount of the filtered difference signal; a first digital-to-analog converter coupled to the quantizer to receive the quantized signal, and configured to generate the first feedback signal according to the quantized signal; and a second D/A converter coupled to the quantizer to receive the overload signal, and configured to generate the second feedback signal according to the overload signal.
摘要翻译：该应用公开了一种Σ-Δ模数转换器。转换器包括：求和级，配置为接收输入信号，并从输入信号中减去第一反馈信号和第二反馈信号以产生差分信号; 耦合到所述求和级的输出节点并被配置为对所述差分信号进行滤波的环路滤波器; 量化器，其耦合到所述环路滤波器的输出节点，并且被配置为量化所滤波的差分信号以产生量化信号，并且根据滤波的差分信号产生过载信号，其中所述过载信号指示所述经滤波的差分信号是否为过载和/或过滤差分信号的过载量; 耦合到所述量化器以接收所述量化信号的第一数模转换器，并且被配置为根据所述量化信号产生所述第一反馈信号; 以及耦合到所述量化器以接收所述过载信号并被配置为根据所述过载信号产生所述第二反馈信号的第二D / A转换器。

2. 发明授权

US06369728B1 Method and system for real-time processing of the recorded PCM data to get the desired full-scale range of values 有权
标题翻译：用于实时处理记录的PCM数据以获得期望的满量程范围的方法和系统
公开(公告)号：US06369728B1
公开(公告)日：2002-04-09
申请号：US09665491
申请日：2000-09-20
申请人： Seng-Khoon Tng , Inging Yang
发明人： Seng-Khoon Tng , Inging Yang
IPC分类号： H03M118
CPC分类号： H04L25/4902 , H03M3/478 , H04B14/062
摘要： A method and apparatus for processing pulse code modulation (PCM) data that do not reach the full dynamic range of a transmission bus. The method and apparatus provide an output processed PCM data having the maximum peak signal allowable by a transmission bus. The output signal limitation is also dependent on a sampling or recording frequency of input signals. In view of the sampling or recording frequency, the invention scales the processing of the PCM data accordingly.
摘要翻译：一种用于处理未达到传输总线的完整动态范围的脉冲编码调制（PCM）数据的方法和装置。该方法和装置提供具有由传输总线允许的最大峰值信号的输出处理的PCM数据。输出信号限制也取决于输入信号的采样或记录频率。鉴于采样或记录频率，本发明相应地缩放PCM数据的处理。

3. 发明申请

US20060092061A1 Continuous-time delta-sigma ADC with programmable input range 有权
标题翻译：具有可编程输入范围的连续时间Δ-ΣADC
公开(公告)号：US20060092061A1
公开(公告)日：2006-05-04
申请号：US11301513
申请日：2005-12-13
申请人： Henrik Jensen
发明人： Henrik Jensen
IPC分类号： H03M3/00
CPC分类号： H03M3/478
摘要： A scaled input current is produced that substantially matches the full scale input of a CTΔΣADC that substantially cancels an offset bias current component of the input current. A variable bias resistance value is coupled between the integrator input and one of a supply voltage and a circuit common. The method further includes integrating the input current to produce an integrated signal representing a time averaged value of the input current to substantially remove noise from a frequency band of interest. The integrated signal is produced to a quantizer to produce a feedback current that substantially cancels a quantization noise component in the digital representation of the scaled analog signal by coupling the digital representation of the scaled analog signal to a programmable digital switch wherein the programmable digital switch either sinks current from or sources current to the integrator input.
摘要翻译：产生缩放的输入电流，其基本上匹配基本上抵消输入电流的偏移偏置电流分量的CTDeltaSigmaADC的满量程输入。可变偏置电阻值耦合在积分器输入和电源电压和电路公共之一之间。该方法还包括积分输入电流以产生表示输入电流的时间平均值的积分信号，以从感兴趣的频带基本上去除噪声。将积分信号产生到量化器，以产生反馈电流，该反馈电流通过将经缩放的模拟信号的数字表示耦合到可编程数字开关，其中可编程数字开关或者是可编程数字开关，基本上消除了缩放的模拟信号的数字表示中的量化噪声分量吸收来自电流的电流或来自积分器输入的电流。

4. 发明授权

US06600789B1 Signal processing method and device 有权
标题翻译：信号处理方法及装置
公开(公告)号：US06600789B1
公开(公告)日：2003-07-29
申请号：US09319232
申请日：1999-06-02
申请人： Lauri Lipasti , Arhippa Kovanen
发明人： Lauri Lipasti , Arhippa Kovanen
IPC分类号： H03M302
CPC分类号： H03M3/478 , H03M3/43 , H03M7/3028 , H03M7/304
摘要： The invention relates to digital signal processing and specifically to level control of a pulse density modulated (PDM) signal generated by a sigma-delta modulator. A single-bit pulse density modulated PDM signal is generated by a first sigma-delta modulator being an analog modulator, for instance. Level control is performed by multiplying the single-bit pulse density modulated PDM signal by a multibit multiplier to obtain a multibit number stream, which is reconverted into a single-bit PDM signal by a second digital sigma-delta modulator, as to the signal-to-noise ratio. Thus the most significant factor in the total signal-to-noise is the noise level of the first sigma-delta modulator, by which the PDM signal was originally generated. In the subsequent second sigma-delta modulator, the PDM signal can then be attenuated as much as is the difference between SNR performance of the modulators without any decrease in the total signal-to-noise ratio. A relative amplification of the PDM signal is provided in this manner.
摘要翻译：本发明涉及数字信号处理，具体涉及由Σ-Δ调制器产生的脉冲密度调制（PDM）信号的电平控制。例如，通过作为模拟调制器的第一Σ-Δ调制器产生单位脉冲密度调制的PDM信号。通过将单位脉冲浓度调制PDM信号乘以多位乘法器来执行电平控制，以获得多位数流，其由第二数字Σ-Δ调制器转换为单位PDM信号，信噪比。因此，总信噪比中最重要的因素是最初产生PDM信号的第一Σ-Δ调制器的噪声电平。在随后的第二个Σ-Δ调制器中，PDM信号可以像调制器的SNR性能之间的差异一样被衰减，而不会降低总的信噪比。以这种方式提供PDM信号的相对放大。

5. 发明授权

US06452521B1 Mapping a delta-sigma converter range to a sensor range 有权
标题翻译：将delta-sigma转换器范围映射到传感器范围
公开(公告)号：US06452521B1
公开(公告)日：2002-09-17
申请号：US09808516
申请日：2001-03-14
申请人： Feng Wang , Michael J. Gaboury
发明人： Feng Wang , Michael J. Gaboury
IPC分类号： H03M162
CPC分类号： H03M3/478
摘要： A mapping circuit coupled to the integrator circuit of a delta-sigma converter to map the analog input range of the integrator to the analog out-put range of the sensor. The integrator circuit provides an integrator output to a controller to generate a digital output, which is in a digital output range representing the analog input range. A sensor input circuit includes a sensor having an analog sensor output range. The mapping circuit is coupled to the integrator circuit and is responsive to control signals from the controller to map the analog input range of the integrator to the analog output range of the sensor.
摘要翻译：耦合到Δ-Σ转换器的积分器电路的映射电路，以将积分器的模拟输入范围映射到传感器的模拟输出范围。积分器电路向控制器提供积分器输出以产生数字输出，该数字输出处于表示模拟输入范围的数字输出范围内。传感器输入电路包括具有模拟传感器输出范围的传感器。映射电路耦合到积分器电路，并且响应于来自控制器的控制信号将积分器的模拟输入范围映射到传感器的模拟输出范围。

6. 发明授权

US5821890A .DELTA..SIGMA. analog-to-digital converter having built-in variable-gain end 失效
标题翻译：具有内置可变增益端的DELTA SIGMA模数转换器
公开(公告)号：US5821890A
公开(公告)日：1998-10-13
申请号：US641935
申请日：1996-05-02
申请人： Daejong Kim , Deog Kyoon Jeong
发明人： Daejong Kim , Deog Kyoon Jeong
IPC分类号： H03M3/02 , H03M7/32 , H03M1/12
CPC分类号： H03M3/478
摘要： A .DELTA..SIGMA. analog-to-digital converter having a built-in variable gain end is disclosed including a .DELTA..SIGMA. analog-to-digital converter portion, the converter portion having an amplifier for amplifying and outputting an input signal, a charging device for accumulating a signal voltage, a plurality of switches coupling the input signal to the charging device and coupling the voltage accumulated in the charging device to the amplifier, and a comparator for producing a HIGH output if the output of the amplifier becomes above a predetermined level, and producing a LOW output if the output of the amplifier becomes below the predetermined level, and an AGC controller both ends of which are coupled to a reference voltage, the controller generating a voltage reduced into 1/N of the reference voltage through switches at respective nodes of a plurality of resistors.
摘要翻译：公开了具有内置可变增益端的DELTA SIGMA模数转换器，其包括DELTA SIGMA模数转换器部分，该转换器部分具有放大和输出输入信号的放大器，用于累加的充电装置信号电压，多个开关将输入信号耦合到充电装置，并将累积在充电装置中的电压耦合到放大器;以及比较器，用于在放大器的输出变得高于预定电平时产生HIGH输出;以及如果放大器的输出变得低于预定电平，则产生低输出，并且两个AGC控制器的两端耦合到参考电压，该控制器通过相应节点上的开关产生降低到基准电压的1 / N的电压的多个电阻器。

7. 发明授权

US07158064B2 Continuous-time delta-sigma ADC with programmable input range 有权
标题翻译：具有可编程输入范围的连续时间Δ-ΣADC
公开(公告)号：US07158064B2
公开(公告)日：2007-01-02
申请号：US11301513
申请日：2005-12-13
申请人： Henrik T. Jensen
发明人： Henrik T. Jensen
IPC分类号： H03M3/00
CPC分类号： H03M3/478
摘要： A scaled input current is produced that substantially matches the full scale input of a CTΔΣADC that substantially cancels an offset bias current component of the input current. A variable bias resistance value is coupled between the integrator input and one of a supply voltage and a circuit common. The method further includes integrating the input current to produce an integrated signal representing a time averaged value of the input current to substantially remove noise from a frequency band of interest. The integrated signal is produced to a quantizer to produce a feedback current that substantially cancels a quantization noise component in the digital representation of the scaled analog signal by coupling the digital representation of the scaled analog signal to a programmable digital switch wherein the programmable digital switch either sinks current from or sources current to the integrator input.
摘要翻译：产生缩放的输入电流，其基本上匹配基本上抵消输入电流的偏移偏置电流分量的CTDeltaSigmaADC的满量程输入。可变偏置电阻值耦合在积分器输入和电源电压和电路公共之一之间。该方法还包括积分输入电流以产生表示输入电流的时间平均值的积分信号，以从感兴趣的频带基本上去除噪声。将积分信号产生到量化器，以产生反馈电流，该反馈电流通过将经缩放的模拟信号的数字表示耦合到可编程数字开关，其中可编程数字开关或者是可编程数字开关，基本上消除了缩放的模拟信号的数字表示中的量化噪声分量从当前流向积分器输入的电流。

8. 发明授权

US06975259B1 Continuous-time delta-sigma ADC with programmable input range 失效
标题翻译：具有可编程输入范围的连续时间Δ-ΣADC
公开(公告)号：US06975259B1
公开(公告)日：2005-12-13
申请号：US10922532
申请日：2004-08-20
申请人： Henrik T. Jensen
发明人： Henrik T. Jensen
IPC分类号： H03M3/00 , H03M3/04 , H03M7/12
CPC分类号： H03M3/478
摘要： A scaled input current is produced that substantially matches the full scale input of a CTΔτADC that substantially cancels an offset bias current component of the input current. A variable bias resistance value is coupled between the integrator input and one of a supply voltage and a circuit common. The method further includes integrating the input current to produce an integrated signal representing a time averaged value of the input current to substantially remove noise from a frequency band of interest. The integrated signal is produced to a quantizer to produce a feedback current that substantially cancels a quantization noise component in the digital representation of the scaled analog signal by coupling the digital representation of the scaled analog signal to a programmable digital switch wherein the programmable digital switch either sinks current from or sources current to the integrator input.
摘要翻译：产生缩放的输入电流，其基本上匹配基本上抵消输入电流的偏移偏置电流分量的CTDeltatauADC的满量程输入。可变偏置电阻值耦合在积分器输入和电源电压和电路公共之一之间。该方法还包括积分输入电流以产生表示输入电流的时间平均值的积分信号，以从感兴趣的频带基本上去除噪声。将积分信号产生到量化器，以产生反馈电流，该反馈电流通过将经缩放的模拟信号的数字表示耦合到可编程数字开关，其中可编程数字开关或者是可编程数字开关，基本上消除了缩放的模拟信号的数字表示中的量化噪声分量从当前流向积分器输入的电流。

9. 发明授权

US09219495B2 Sigma-delta analog-to-digital converter 有权
标题翻译： Sigma-delta模数转换器
公开(公告)号：US09219495B2
公开(公告)日：2015-12-22
申请号：US14659639
申请日：2015-03-17
申请人： MONTAGE TECHNOLOGY (SHANGHAI) CO., LTD.
发明人： Xiaomin Si
IPC分类号： H03M3/00 , H03M1/00 , H03M1/12 , H04L25/03
CPC分类号： H03M3/464 , H03M1/00 , H03M1/12 , H03M3/30 , H03M3/322 , H03M3/424 , H03M3/454 , H03M3/478 , H04L25/03038
摘要： The application disclose a sigma-delta analog-to-digital converter. The converter comprises: a summing stage, configured to receive an input signal and subtract a first feedback signal and a second feedback signal from the input signal to generate a difference signal; a loop filter coupled to an output node of the summing stage, and configured to filter the difference signal; a quantizer coupled to an output node of the loop filter, and configured to quantize the filtered difference signal to generate a quantized signal, and to generate an overload signal according to the filtered difference signal, wherein the overload signal indicates whether the filtered difference signal is overloaded and/or an overload amount of the filtered difference signal; a first digital-to-analog converter coupled to the quantizer to receive the quantized signal, and configured to generate the first feedback signal according to the quantized signal; and a second D/A converter coupled to the quantizer to receive the overload signal, and configured to generate the second feedback signal according to the overload signal.
摘要翻译：该应用公开了一种Σ-Δ模数转换器。转换器包括：求和级，配置为接收输入信号，并从输入信号中减去第一反馈信号和第二反馈信号以产生差分信号; 耦合到所述求和级的输出节点并被配置为对所述差分信号进行滤波的环路滤波器; 量化器，其耦合到所述环路滤波器的输出节点，并且被配置为量化所滤波的差分信号以产生量化信号，并且根据滤波的差分信号产生过载信号，其中所述过载信号指示滤波的差分信号是否为过载和/或过滤差分信号的过载量; 耦合到所述量化器以接收所述量化信号的第一数模转换器，并且被配置为根据所述量化信号产生所述第一反馈信号; 以及耦合到所述量化器以接收所述过载信号并被配置为根据所述过载信号产生所述第二反馈信号的第二D / A转换器。

10. 发明授权

US06847920B2 Approximation sequence processing 有权
标题翻译：近似序列处理
公开(公告)号：US06847920B2
公开(公告)日：2005-01-25
申请号：US10630356
申请日：2003-07-30
申请人： David S. McGrath
发明人： David S. McGrath
IPC分类号： G06F17/17 , H03M3/00 , H04B1/00
CPC分类号： G06F17/17 , H03M3/478
摘要： A method of producing an approximation sequence to a series of sample values, the method comprising the steps of (a) determining a first set having candidate partial sequences as members, each member comprising a plurality of elements; (b) selecting the first n elements of one of the members of the first set as a next output element for said approximation sequence; n a positive integer; (c) forming a second set having descendent candidate partial sequences as members from said first set; (d) applying a fitness filtering process to said second set to rank its members according to fitness for representing at least a corresponding portion of the series of input samples; (e) selecting at least some of the members of the second set to form a third set; and repeating steps (a) to (e) so as to produce said approximation sequence, wherein the third set of step (e) functions as the first set of the subsequent step (a).
摘要翻译：一种对一系列样本值产生近似序列的方法，所述方法包括以下步骤：（a）确定具有候选部分序列作为成员的第一集合，每个部件包括多个元素; （b）选择第一组成员之一的前n个元素作为所述近似序列的下一个输出元素; n为正整数; （c）形成具有来自所述第一组的成员的后代候选部分序列的第二集合; （d）对所述第二集合应用适应度滤波处理，以根据适于表示所述一系列输入样本的至少相应部分的适合度对其成员进行排序; （e）选择第二组的至少一些成员以形成第三组; 以及重复步骤（a）至（e）以产生所述近似序列，其中步骤（e）的第三组用作随后步骤（a）的第一组。

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