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1. 发明授权

US08081017B2 Clock signal frequency dividing circuit and clock signal frequency dividing method 有权
标题翻译：时钟信号分频电路和时钟信号分频方式
公开(公告)号：US08081017B2
公开(公告)日：2011-12-20
申请号：US12515901
申请日：2007-11-09
申请人： Atsufumi Shibayama , Koichi Nose
发明人： Atsufumi Shibayama , Koichi Nose
IPC分类号： H03K21/00
CPC分类号： H03K23/48 , G06F1/08 , H03K23/667
摘要： To provide a rational frequency dividing circuit wherein the variations in cycle times of frequency divided clock signals are small, there are many occasions in which the minimum cycle time of frequency divided clock signals and test costs are small. A clock signal frequency dividing circuit, the frequency division ratio of which is specified as N/M where are both N and M are integers, includes an output clock selecting circuit (200) that selects one of three situations: an input clock signal is outputted as it is, the input clock signal is inverted and outputted and the input clock signal is not outputted; and a clock selection control circuit (100) that generates a control signal for controlling the foregoing selection of the output clock selecting circuit. The clock selection control circuit controls the foregoing selection of the output clock selecting circuit at every cycle of the input clock signal.
摘要翻译：为了提供一种合理的分频电路，其中分频时钟信号的周期时间的变化小，在分频时钟信号和测试成本的最小周期时间很少的场合很多。其分频比被指定为N / M的时钟信号分频电路都是N和M都是整数，包括选择三种情况之一的输出时钟选择电路（200）：输出输入时钟信号输入时钟信号被反相输出，不输出输入时钟信号; 以及时钟选择控制电路（100），其产生用于控制输出时钟选择电路的上述选择的控制信号。时钟选择控制电路在输入时钟信号的每个周期控制输出时钟选择电路的上述选择。

2. 发明授权

US07671635B2 Frequency synthesizer, coupled divide-by-N circuit, current-reuse multiply-by-M circuit 有权
标题翻译：频率合成器，N分频耦合电路，电流复用乘法电路
公开(公告)号：US07671635B2
公开(公告)日：2010-03-02
申请号：US11961130
申请日：2007-12-20
申请人： Che-Wei Fan , Shen-Iuan Liu
发明人： Che-Wei Fan , Shen-Iuan Liu
IPC分类号： H03B21/00
CPC分类号： H03L7/183 , G06F7/68 , H03K23/48
摘要： A frequency synthesizer is provided in the present invention. The frequency synthesizer includes a single phase-locked loop having a reference frequency signal input, a first output, a second output and a pair of divide-by-N circuits coupled with each other and electrically connected to the second output; a multiply-by-M circuit having a first input electrically connected to the first output and a third output; and a combination of a buffer and a mixer having a second input electrically connected to the second output and a third input electrically connected to the third output generating a frequency signal output.
摘要翻译：在本发明中提供了频率合成器。频率合成器包括具有参考频率信号输入，第一输出，第二输出和一对分压N电路的单个锁相环，彼此耦合并电连接到第二输出; 具有与第一输出电连接的第一输入和第三输出的乘法电路; 以及缓冲器和混合器的组合，其具有电连接到第二输出端的第二输入端和电连接到第三输出端的产生频率信号输出的第三输入端。

3. 发明授权

US07512208B2 Digital clock divider 失效
标题翻译：数字时钟分频器
公开(公告)号：US07512208B2
公开(公告)日：2009-03-31
申请号：US11891300
申请日：2007-08-09
申请人： Carsten Noeske
发明人： Carsten Noeske
IPC分类号： H03K21/00
CPC分类号： H03K23/48
摘要： A digital clock divider includes an adder and a clock division device configured to receive a first clock signal with a first frequency and to output a second clock signal having a lower frequency relative to the first frequency. The digital clock divider also includes a division value separation device and a feedback section. The division value separation device is configured to divide an addition value output from the adder into an integer value and a fractional value. The feedback section is configured to provide to the adder a feedback value, the feedback value comprising the fractional component or the fractional component modified by a processing device. The adder is configured to add the feedback value to an applied division value. The clock division device is controlled on the basis of the integer value.
摘要翻译：数字时钟分频器包括加法器和时钟分频装置，其被配置为接收具有第一频率的第一时钟信号并输出相对于第一频率具有较低频率的第二时钟信号。数字时钟分频器还包括分频值分离装置和反馈部分。分割值分离装置被配置为将从加法器输出的加法值分成整数值和分数值。反馈部分被配置为向加法器提供反馈值，反馈值包括由处理装置修改的分数分量或分数分量。加法器被配置为将反馈值添加到所应用的除法值。时钟分频装置是以整数值为基础进行控制的。

4. 发明申请

US20100052740A1 CLOCK SIGNAL FREQUENCY DIVIDING CIRCUIT AND CLOCK SIGNAL FREQUENCY DIVIDING METHOD 有权
标题翻译：时钟信号分频电路和时钟信号频分法
公开(公告)号：US20100052740A1
公开(公告)日：2010-03-04
申请号：US12515901
申请日：2007-11-09
申请人： Atsufumi Shibayama , Koichi Nose
发明人： Atsufumi Shibayama , Koichi Nose
IPC分类号： H03B19/00
CPC分类号： H03K23/48 , G06F1/08 , H03K23/667
摘要： To provide a rational frequency dividing circuit wherein the variations in cycle times of frequency divided clock signals are small, there are many occasions in which the minimum cycle time of frequency divided clock signals and test costs are small. A clock signal frequency dividing circuit, the frequency division ratio of which is specified as N/M where are both N and Mare integers, includes an output clock selecting circuit (200) that selects one of three situations: an input clock signal is outputted as it is, the input clock signal is inverted and outputted and the input clock signal is not outputted; and a clock selection control circuit (100) that generates a control signal for controlling the foregoing selection of the output clock selecting circuit. The clock selection control circuit controls the foregoing selection of the output clock selecting circuit at every cycle of the input clock signal.
摘要翻译：为了提供一种合理的分频电路，其中分频时钟信号的周期时间的变化小，在分频时钟信号和测试成本的最小周期时间很少的场合很多。其分频比被指定为N / M的时钟信号分频电路均为N和Mare整数，包括选择三种情况之一的输出时钟选择电路（200）：输入时钟信号作为输入时钟信号被反相输出，输入时钟信号不输出; 以及时钟选择控制电路（100），其生成用于控制输出时钟选择电路的上述选择的控制信号。时钟选择控制电路在输入时钟信号的每个周期控制输出时钟选择电路的上述选择。

5. 发明申请

US20080136471A1 Generating an Output Signal With a Frequency That is a Non-Integer Fraction of an Input Signal 有权
标题翻译：以输入信号的非整数分数的频率生成输出信号
公开(公告)号：US20080136471A1
公开(公告)日：2008-06-12
申请号：US11609347
申请日：2006-12-12
申请人： Anant Shankar Kamath
发明人： Anant Shankar Kamath
IPC分类号： H03L7/081 , H03K21/00
CPC分类号： H03K23/48 , H03L7/0812 , H03L7/16
摘要： Generating an output signal having a frequency of 1/(M+F) of the frequency of the input signal, wherein M represents an integer and F represents a non-zero fraction. Assuming F equals (Q/R) in one embodiment, wherein Q and R are integers, R intermediate signals phase shifted by equal degree (relative to the one with closest phase shift) in one clock period of the input signal are generated. A selection circuit may select one of the intermediate signals in one clock cycle, select the successive signals with increasing phase shift in Q clock cycles, and leave the intermediate signal with the same shift as in the previous clock cycle in the remaining ones of the M clock cycles. A counter counts a change of state in the output of the selection circuit, and generates a pulse representing an edge of the output signal at the time instance when counter counts M.
摘要翻译：产生具有输入信号频率的1 /（M + F）频率的输出信号，其中M表示整数，F表示非零分数。假设在一个实施例中，F等于（Q / R），其中Q和R是整数，产生在输入信号的一个时钟周期内相移相等程度（相对于最接近的相移的）中间信号。选择电路可以在一个时钟周期中选择一个中间信号，在Q个时钟周期中选择具有增加的相移的连续信号，并且使剩余的M中的与上一个时钟周期相同的移位的中间信号时钟周期。计数器对选择电路的输出中的状态变化进行计数，并且在计数器计数M的时间点产生表示输出信号的边沿的脉冲。

6. 发明授权

US07560962B2 Generating an output signal with a frequency that is a non-integer fraction of an input signal 有权
$Generating an output signal with a frequency that is a non-integer fraction of an input signal$
标题翻译：以输入信号的非整数分数的频率生成输出信号
公开(公告)号：US07560962B2
公开(公告)日：2009-07-14
申请号：US11609347
申请日：2006-12-12
申请人： Anant Shankar Kamath
发明人： Anant Shankar Kamath
IPC分类号： H03L7/06
CPC分类号： H03K23/48 , H03L7/0812 , H03L7/16
摘要： Generating an output signal having a frequency of 1/(M+F) of the frequency of the input signal, wherein M represents an integer and F represents a non-zero fraction. Assuming F equals (Q/R) in one embodiment, wherein Q and R are integers, R intermediate signals phase shifted by equal degree (relative to the one with closest phase shift) in one clock period of the input signal are generated. A selection circuit may select one of the intermediate signals in one clock cycle, select the successive signals with increasing phase shift in Q clock cycles, and leave the intermediate signal with the same shift as in the previous clock cycle in the remaining ones of the M clock cycles. A counter counts a change of state in the output of the selection circuit, and generates a pulse representing an edge of the output signal at the time instance when counter counts M.
摘要翻译：产生具有输入信号频率的1 /（M + F）频率的输出信号，其中M表示整数，F表示非零分数。假设在一个实施例中，F等于（Q / R），其中Q和R是整数，产生在输入信号的一个时钟周期内相移相等程度（相对于最接近的相移的）中间信号。选择电路可以在一个时钟周期中选择一个中间信号，在Q个时钟周期中选择具有增加的相移的连续信号，并且使剩余的M中的与上一个时钟周期相同的移位的中间信号时钟周期。计数器对选择电路的输出中的状态变化进行计数，并且在计数器计数M的时间点产生表示输出信号的边沿的脉冲。

7. 发明申请

US20090067563A1 FREQUENCY SYNTHESIZER, COUPLED DIVIDE-BY-N CIRCUIT, CURRENT-REUSE MULTIPLY-BY-M CIRCUIT 有权
标题翻译：频率合成器，联合分流电路，电流 - 多路复用电路
公开(公告)号：US20090067563A1
公开(公告)日：2009-03-12
申请号：US11961130
申请日：2007-12-20
申请人： Che-Wei Fan , Shen-Iuan Liu
发明人： Che-Wei Fan , Shen-Iuan Liu
IPC分类号： H03D3/24
CPC分类号： H03L7/183 , G06F7/68 , H03K23/48
摘要： A frequency synthesizer is provided in the present invention. The frequency synthesizer includes a single phase-locked loop having a reference frequency signal input, a first output, a second output and a pair of divide-by-N circuits coupled with each other and electrically connected to the second output; a multiply-by-M circuit having a first input electrically connected to the first output and a third output; and a combination of a buffer and a mixer having a second input electrically connected to the second output and a third input electrically connected to the third output generating a frequency signal output.
摘要翻译：在本发明中提供了频率合成器。频率合成器包括具有参考频率信号输入，第一输出，第二输出和一对分压N电路的单个锁相环，彼此耦合并电连接到第二输出; 具有与第一输出电连接的第一输入和第三输出的乘法电路; 以及缓冲器和混合器的组合，其具有电连接到第二输出端的第二输入端和电连接到第三输出端的产生频率信号输出的第三输入端。

8. 发明申请

US20080040627A1 Digital clock divider 失效
标题翻译：数字时钟分频器
公开(公告)号：US20080040627A1
公开(公告)日：2008-02-14
申请号：US11891300
申请日：2007-08-09
申请人： Carsten Noeske
发明人： Carsten Noeske
IPC分类号： G06F1/04
CPC分类号： H03K23/48
摘要： Digital Clock Divider and Method for Operating a Digital Clock Divider A digital clock divider includes an adder and a clock division device configured to receive a first clock signal with a first frequency and to output a second clock signal having a lower frequency relative to the first frequency. The digital clock divider also includes a division value separation device and a feedback section. The division value separation device is configured to divide an addition value output from the adder into an integer value and a fractional value. The feedback section is configured to provide to the adder a feedback value, the feedback value comprising the fractional component or the fractional component modified by a processing device. The adder is configured to add the feedback value to an applied division value. The clock division device is controlled on the basis of the integer value.
摘要翻译：用于操作数字时钟分频器的数字时钟分频器和方法数字时钟分频器包括加法器和时钟分频装置，其被配置为接收具有第一频率的第一时钟信号，并输出相对于第一频率具有较低频率的第二时钟信号。数字时钟分频器还包括分频值分离装置和反馈部分。分割值分离装置被配置为将从加法器输出的加法值分成整数值和分数值。反馈部分被配置为向加法器提供反馈值，反馈值包括由处理装置修改的分数分量或分数分量。加法器被配置为将反馈值添加到所应用的除法值。时钟分频装置是以整数值为基础进行控制的。

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