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1. 发明申请

US20160049923A1 DIGITAL FILTER 审中-公开
标题翻译：数字滤波器
公开(公告)号：US20160049923A1
公开(公告)日：2016-02-18
申请号：US14925895
申请日：2015-10-28
申请人： Intel Deutschland GmbH
发明人： Andreas Menkhoff
IPC分类号： H03H17/02
CPC分类号： H03H17/028 , H03H17/0433
摘要： Methods and apparatuses in which a first stage of a digital filter receives input data to be filtered, the first stage of a digital filter operating at a first clock; a second stage of the digital filter outputs filtered output data, the second stage of the digital filter operating on a second clock, wherein a ratio of a frequency of the first clock and a frequency of the second clock is a fractional number, and a frequency of the second clock is higher than a frequency of the first clock; the first stage receives an indication of a ratio of the first clock and the second clock; and the first stage receives an indication of a time offset between (1) a clock pulse of the second clock, which occurs between a first clock pulse and a second clock pulse of the first clock, and (2) the first clock pulse of the first clock.
摘要翻译：数字滤波器的第一级接收要滤波的输入数据，在第一时钟操作的数字滤波器的第一级的方法和装置; 数字滤波器的第二级输出滤波输出数据，数字滤波器的第二级在第二时钟上工作，其中第一时钟的频率与第二时钟的频率的比率是小数，频率的第二时钟的频率高于第一时钟的频率; 第一级接收第一时钟和第二时钟的比率的指示; 并且第一级接收在（1）在第一时钟的第一时钟脉冲和第一时钟脉冲之间发生的第二时钟的时钟脉冲之间的时间偏移的指示，以及（2）第一时钟的第一时钟脉冲第一时钟

2. 发明授权

US07908306B1 SRC with multiple sets of filter coefficients in memory and a high order coefficient interpolator 有权
标题翻译：存储器中具有多组滤波器系数的SRC和高阶系数内插器
公开(公告)号：US07908306B1
公开(公告)日：2011-03-15
申请号：US10805596
申请日：2004-03-19
申请人： Daniel L. W. Chieng , Jack B. Andersen , Larry E. Hand
发明人： Daniel L. W. Chieng , Jack B. Andersen , Larry E. Hand
IPC分类号： G06F17/10
CPC分类号： H03H17/0294 , H03F3/217 , H03H17/0275 , H03H17/0292 , H03H17/0433 , H03H17/0455
摘要： Systems and methods for converting a data stream from a first sample rate to a second sample rate using a sample rate converter that employs selectable filters. In one embodiment, the filters are implemented by providing multiple sets of filter coefficients in a memory, selecting one of the sets of filter coefficients and performing coefficient interpolation to produce filter coefficients that are convolved with the input data stream to produce a re-sampled output data stream. The input signal can be an audio signal that is convolved with interpolated polyphase filter coefficients in the sample rate converter of a digital PWM audio amplifier. The set of filter coefficients can be selected by a value stored in a filter selection register that is modifiable by a DSP or by user input. The sets of filter coefficients can be stored in a single memory and interpolated according to a cubic spline interpolation algorithm.
摘要翻译：用于使用采用可选择滤波器的采样率转换器将数据流从第一采样率转换为第二采样率的系统和方法。在一个实施例中，通过在存储器中提供多组滤波器系数来实现滤波器，选择滤波器系数集合中的一个并执行系数插值以产生与输入数据流卷积的滤波器系数，以产生再采样输出数据流。输入信号可以是在数字PWM音频放大器的采样率转换器中与内插多相滤波器系数进行卷积的音频信号。滤波器系数的集合可以通过存储在滤波器选择寄存器中的值来选择，该值可由DSP或用户输入来修改。滤波器系数组可以存储在单个存储器中，并根据三次样条插值算法进行内插。

3. 发明授权

US07312729B2 Universal sampling rate converter in electronic devices and methods 有权
标题翻译：电子设备通用采样率转换器及方法
公开(公告)号：US07312729B2
公开(公告)日：2007-12-25
申请号：US10919819
申请日：2004-08-17
申请人： Daniela Radakovic
发明人： Daniela Radakovic
IPC分类号： H03M7/00
CPC分类号： H03H17/0416 , H03H17/0282 , H03H17/0433
摘要： A method and apparatus for converting the sampling rate of digital signals including a decimating comprising a low pass filter (122) and a downsampler (124), wherein the input signal is decimated a number of times based on a ratio of an input sampling rate to an output sampling rate. The exemplary apparatus also includes an upsampler (130) and another decimator (140) wherein the signal is upsampled after decimating if a ratio of the input sampling rate to an output sampling rate is not a power of an integer number.
摘要翻译：一种用于转换数字信号的采样率的方法和装置，包括包括低通滤波器（122）和下采样器（124）的抽取，其中输入信号基于输入采样率与输出采样率。示例性装置还包括上采样器（130）和另一抽取器（140），其中如果输入采样率与输出采样率的比率不是整数的幂，则抽取后信号被上采样。

4. 发明申请

US20060039514A1 Universal sampling rate converter in electronic devices and methods 有权
标题翻译：电子设备通用采样率转换器及方法
公开(公告)号：US20060039514A1
公开(公告)日：2006-02-23
申请号：US10919819
申请日：2004-08-17
申请人： Daniela Radakovic
发明人： Daniela Radakovic
IPC分类号： H04L7/00
CPC分类号： H03H17/0416 , H03H17/0282 , H03H17/0433
摘要： A method and apparatus for converting the sampling rate of digital signals including a decimating comprising a low pass filter (122) and a downsampler (124), wherein the input signal is decimated a number of times based on a ratio of an input sampling rate to an output sampling rate. The exemplary apparatus also includes an upsampler (130) and another decimator (140) wherein the signal is upsampled after decimating if a ratio of the input sampling rate to an output sampling rate is not a power of an integer number.
摘要翻译：一种用于转换数字信号的采样率的方法和装置，包括包括低通滤波器（122）和下采样器（124）的抽取，其中输入信号基于输入采样率与输出采样率。示例性装置还包括上采样器（130）和另一抽取器（140），其中如果输入采样率与输出采样率的比率不是整数的幂，则抽取后信号被上采样。

5. 发明授权

US10009013B2 Digital filter 有权
公开(公告)号：US10009013B2
公开(公告)日：2018-06-26
申请号：US14925895
申请日：2015-10-28
申请人： Intel Deutschland GmbH
发明人： Andreas Menkhoff
IPC分类号： G06F17/10 , H03H17/02 , H03H17/04
CPC分类号： H03H17/028 , H03H17/0433
摘要： A first stage of a digital filter received input data to be filtered, the first stage of a digital filter operating at a first clock; a second stage of the digital filter outputs filtered output data, the second stage of the digital filter operating on a second clock, wherein a ratio of a frequency of the first clock and a frequency of the second clock is a fractional number, and a frequency of the second clock is higher than a frequency of the first clock; the first stage receives an indication of a ratio of the first clock and the second clock; and the first stage receives an indication of a time offset between (1) a clock pulse of the second clock, which occurs between a first clock pulse and (2) the first clock pulse of the first clock.

6. 发明授权

US09190983B2 Digital filter 有权
标题翻译：数字滤波器
公开(公告)号：US09190983B2
公开(公告)日：2015-11-17
申请号：US13591516
申请日：2012-08-22
申请人： Andreas Menkhoff
发明人： Andreas Menkhoff
IPC分类号： G06F17/10 , H03H17/04 , H03H17/02
CPC分类号： H03H17/028 , H03H17/0433
摘要： A first stage of a digital filter receives input data to be filtered, the first stage of a digital filter operating at a first clock; a second stage of the digital filter outputs filtered output data, the second stage of the digital filter operating on a second clock, wherein a ratio of a frequency of the first clock and a frequency of the second clock is a fractional number, and a frequency of the second clock is higher than a frequency of the first clock; the first stage receives an indication of a ratio of the first clock and the second clock; and the first stage receives an indication of a time offset between (1) a clock pulse of the second clock, which occurs between a first clock pulse and a second clock pulse of the first clock, and (2) the first clock pulse of the first clock.
摘要翻译：数字滤波器的第一级接收要被滤波的输入数据，在第一时钟操作的数字滤波器的第一级; 数字滤波器的第二级输出滤波输出数据，数字滤波器的第二级在第二时钟上工作，其中第一时钟的频率与第二时钟的频率的比率是小数，频率的第二时钟的频率高于第一时钟的频率; 第一级接收第一时钟和第二时钟的比率的指示; 并且第一级接收在（1）在第一时钟的第一时钟脉冲和第一时钟脉冲之间发生的第二时钟的时钟脉冲之间的时间偏移的指示，以及（2）第一时钟的第一时钟脉冲第一时钟

7. 发明申请

US20100057821A1 Digital Filter 有权
标题翻译：数字滤波器
公开(公告)号：US20100057821A1
公开(公告)日：2010-03-04
申请号：US12201465
申请日：2008-08-29
申请人： Andreas Menkhoff
发明人： Andreas Menkhoff
IPC分类号： G06F17/10
CPC分类号： H03H17/028 , H03H17/0433
摘要： Methods and apparatuses in which a first stage of a digital filter receives input data to be filtered, the first stage of a digital filter operating at a first clock; a second stage of the digital filter outputs filtered output data, the second stage of the digital filter operating on a second clock, wherein a ratio of a frequency of the first clock and a frequency of the second clock is a fractional number, and a frequency of the second clock is higher than a frequency of the first clock; the first stage receives an indication of a ratio of the first clock and the second clock; and the first stage receives an indication of a time offset between (1) a clock pulse of the second clock, which occurs between a first clock pulse and a second clock pulse of the first clock, and (2) the first clock pulse of the first clock.
摘要翻译：数字滤波器的第一级接收要滤波的输入数据，在第一时钟操作的数字滤波器的第一级的方法和装置; 数字滤波器的第二级输出滤波输出数据，数字滤波器的第二级在第二时钟上工作，其中第一时钟的频率与第二时钟的频率的比率是小数，频率的第二时钟的频率高于第一时钟的频率; 第一级接收第一时钟和第二时钟的比率的指示; 并且第一级接收在（1）在第一时钟的第一时钟脉冲和第一时钟脉冲之间发生的第二时钟的时钟脉冲之间的时间偏移的指示，以及（2）第一时钟的第一时钟脉冲第一时钟

8. 发明申请

US20160180860A1 High order B-spline sampling rate conversion (SRC) 审中-公开
标题翻译：高阶B样条采样率转换（SRC）
公开(公告)号：US20160180860A1
公开(公告)日：2016-06-23
申请号：US14757801
申请日：2015-12-23
申请人： QUALCOMM Incorporated
发明人： Minsheng Wang
IPC分类号： G10L19/06 , G10L19/26 , G10L19/02
CPC分类号： G10L19/06 , G10L19/02 , G10L19/26 , H03H17/028 , H03H17/0433 , H03H17/0455 , H03H17/0642 , H03H17/0685
摘要： A method for performing a spline interpolation to up-sample audio data includes up-sampling an input audio signal to generate a first signal having a first frequency. The input audio signal is sampled at an input frequency. The method also includes interpolating data of the first signal to generate a second signal having a second frequency. The data of the first signal is interpolated based on a B-spline interpolation function having at least a fourth order. The method includes down-sampling the second signal to generate an output audio signal having an output frequency. The method further includes updating a time index based on an integer operation that is immune to quantization error for a finite-word length implementation.
摘要翻译：用于对上采样音频数据执行样条插值的方法包括对输入音频信号进行上采样以产生具有第一频率的第一信号。输入音频信号以输入频率进行采样。该方法还包括内插第一信号的数据以产生具有第二频率的第二信号。基于具有至少四阶的B样条插值函数来内插第一信号的数据。该方法包括对第二信号进行下采样以产生具有输出频率的输出音频信号。该方法还包括基于对有限字长度实现的量化误差免疫的整数运算来更新时间索引。

9. 发明申请

US20120331026A1 Digital Filter 有权
标题翻译：数字滤波器
公开(公告)号：US20120331026A1
公开(公告)日：2012-12-27
申请号：US13591516
申请日：2012-08-22
申请人： Andreas Menkhoff
发明人： Andreas Menkhoff
IPC分类号： G06F17/10
CPC分类号： H03H17/028 , H03H17/0433
摘要： A first stage of a digital filter receives input data to be filtered, the first stage of a digital filter operating at a first clock; a second stage of the digital filter outputs filtered output data, the second stage of the digital filter operating on a second clock, wherein a ratio of a frequency of the first clock and a frequency of the second clock is a fractional number, and a frequency of the second clock is higher than a frequency of the first clock; the first stage receives an indication of a ratio of the first clock and the second clock; and the first stage receives an indication of a time offset between (1) a clock pulse of the second clock, which occurs between a first clock pulse and a second clock pulse of the first clock, and (2) the first clock pulse of the first clock.
摘要翻译：数字滤波器的第一级接收要被滤波的输入数据，在第一时钟操作的数字滤波器的第一级; 数字滤波器的第二级输出滤波输出数据，数字滤波器的第二级在第二时钟上工作，其中第一时钟的频率与第二时钟的频率的比率是小数，频率的第二时钟的频率高于第一时钟的频率; 第一级接收第一时钟和第二时钟的比率的指示; 并且第一级接收在（1）在第一时钟的第一时钟脉冲和第一时钟脉冲之间发生的第二时钟的时钟脉冲之间的时间偏移的指示，以及（2）第一时钟的第一时钟脉冲第一时钟

10. 发明授权

US08271568B2 Digital filter 有权
标题翻译：数字滤波器
公开(公告)号：US08271568B2
公开(公告)日：2012-09-18
申请号：US12201465
申请日：2008-08-29
申请人： Andreas Menkhoff
发明人： Andreas Menkhoff
IPC分类号： G06F17/17
CPC分类号： H03H17/028 , H03H17/0433
摘要： Methods and apparatuses in which a first stage of a digital filter receives input data to be filtered, the first stage of a digital filter operating at a first clock; a second stage of the digital filter outputs filtered output data, the second stage of the digital filter operating on a second clock, wherein a ratio of a frequency of the first clock and a frequency of the second clock is a fractional number, and a frequency of the second clock is higher than a frequency of the first clock; the first stage receives an indication of a ratio of the first clock and the second clock; and the first stage receives an indication of a time offset between (1) a clock pulse of the second clock, which occurs between a first clock pulse and a second clock pulse of the first clock, and (2) the first clock pulse of the first clock.
摘要翻译：数字滤波器的第一级接收要滤波的输入数据，在第一时钟操作的数字滤波器的第一级的方法和装置; 数字滤波器的第二级输出滤波输出数据，数字滤波器的第二级在第二时钟上工作，其中第一时钟的频率与第二时钟的频率的比率是小数，频率的第二时钟的频率高于第一时钟的频率; 第一级接收第一时钟和第二时钟的比率的指示; 并且第一级接收在（1）在第一时钟的第一时钟脉冲和第一时钟脉冲之间发生的第二时钟的时钟脉冲之间的时间偏移的指示，以及（2）第一时钟的第一时钟脉冲第一时钟

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