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1. 发明授权

US08655936B2 System and method for processing a signal with a filter employing FIR and IIR elements 有权
标题翻译：使用FIR和IIR元件的滤波器处理信号的系统和方法
公开(公告)号：US08655936B2
公开(公告)日：2014-02-18
申请号：US13001042
申请日：2009-06-23
申请人： William Martin Snelgrove
发明人： William Martin Snelgrove
IPC分类号： G06F17/10
CPC分类号： H03H9/46 , H03H17/0219 , H03H17/0288
摘要： A system and method for processing a signal with a filter employing FIR and/or IIR elements. The required controller function is decomposed into primary FIR and/or IIR elements and a compensation filter is provided to address the latency in the primary elements, which would result in undesired operation of the filter. Several configurations of suitable filters are discussed, including multi-rate filters and filters with reduced power requirements.
摘要翻译：一种使用FIR和/或IIR元件的滤波器处理信号的系统和方法。所需的控制器功能被分解成主FIR和/或IIR元件，并且提供补偿滤波器以解决主要元件中的延迟，这将导致滤波器的不期望的操作。讨论了适当滤波器的几种配置，包括具有降低的功率要求的多速率滤波器和滤波器。

2. 发明授权

US07117235B2 Digital decimation filter having finite impulse response (FIR) decimation stages 有权
标题翻译：具有有限脉冲响应（FIR）抽取级的数字抽取滤波器
公开(公告)号：US07117235B2
公开(公告)日：2006-10-03
申请号：US10289485
申请日：2002-11-06
申请人： Richard Hollingsworth Cannon
发明人： Richard Hollingsworth Cannon
IPC分类号： G06F17/17
CPC分类号： H03H17/0288 , H03H17/0664 , H03H17/0671
摘要： A digital decimation filter having Finite Impulse Response (FIR) decimation stages provides improved performance over a Hogenauer decimating filter. The filter comprises multiple integrator stages followed by multiple FIR decimating stages. The zeros of the filter are tunable by adjusting the integer coefficients of the FIR stages providing tunability of the cut-off response, as opposed to the fixed sinc response of the Hogenauer filter. As a result, the number of required stages for a particular steepness is reduced, dramatically reducing the amount of digital circuitry required to implement a particular filter design. The improved filter is especially suitable for use in digital intermediate frequency (IF) stages in receivers, and for code-based applications where selectable decimation rate is desired and a fast multiply is not available.
摘要翻译：具有有限脉冲响应（FIR）抽取级的数字抽取滤波器提供了比Hogenau抽取滤波器更好的性能。滤波器包括多个积分器级，随后是多个FIR抽取级。通过调整FIR阶段的整数系数可以调节滤波器的零点，提供截止响应的可调性，而不是Hogenauer滤波器的固定sinc响应。因此，特定陡度的所需级数减少，从而显着减少了实现特定滤波器设计所需的数字电路的数量。改进的滤波器特别适用于接收机中的数字中频（IF）级，以及用于需要可选择抽取速率且快速乘法不可用的基于代码的应用。

3. 发明申请

US20040260737A1 Time discrete filter comprising upsampling, sampling rate conversion and downsampling stages 有权
标题翻译：时间离散滤波器，包括上采样，采样率转换和下采样阶段
公开(公告)号：US20040260737A1
公开(公告)日：2004-12-23
申请号：US10495583
申请日：2004-05-14
发明人： Adrianus Wilhelmus Maria Van Den Enden , Marc Victor Arends
IPC分类号： G06F017/10
CPC分类号： H03H17/0276 , H03H17/0288 , H03H17/045 , H03H17/0657 , H03H17/0664 , H03H17/0685
摘要： A time discrete filter comprises a sampling rate converter provided with an input and an output, and a down-sampler having a down-sampling factor nd. The time discrete filter further comprises an up-sampler having an up-sampling factor nu, whereby the up-sampler is coupled to the converter input, and the converter output is coupled to the down-sampler. It has been found that if a sampling rate conversion operation is preceded by an up-sampling operation and only after the conversion is followed by a down-sampling operation to a wanted sampling frequency, that then the complexity in terms of the ultimate number of calculations, in particular multiplications and additions, is reduced. This leads to a decrease of the number of instructions per second which is a measure for the complexity of a Digital Signal Processing (DSP) algorithm. In addition this leads to an associated decrease of power consumed by a DSP, such as applied in for example audio, video, and (telecommunication devices, as well as radio and television apparatus.
摘要翻译：时间离散滤波器包括具有输入和输出的采样率转换器和具有下采样因子nd的下采样器。时间离散滤波器还包括具有上采样因子nu的上采样器，由此上取样器耦合到转换器输入，并且转换器输出耦合到下采样器。已经发现，如果采样率转换操作之前是上采样操作，并且仅在转换之后是对所需采样频率的下采样操作，那么在最终计算数量方面的复杂性，特别是乘法和加法，减少了。这导致每秒指令数量的减少，这是数字信号处理（DSP）算法的复杂度的度量。此外，这导致DSP所消耗的功率相关联的降低，例如应用于例如音频，视频和（电信设备以及无线电和电视设备）中。

4. 发明申请

US20040021595A1 Method and system for implementing a sigma delta analog-to-digital converter 有权
标题翻译：用于实现Σ-Δ模数转换器的方法和系统
公开(公告)号：US20040021595A1
公开(公告)日：2004-02-05
申请号：US10321509
申请日：2002-12-18
发明人： Alper Tunga Erdogan , Chung-Li Lu , Bijit Halder
IPC分类号： H03M001/66
CPC分类号： H04L1/0057 , H03H17/0288 , H03M13/235 , H03M13/253 , H03M13/256 , H03M13/2936 , H04L1/0041 , H04L1/0042 , H04L1/0045 , H04L1/0047 , H04L1/0059 , H04L1/006 , H04L25/03063 , H04L27/02 , H04L27/2608 , H04L27/3405 , H04L27/3433 , H04L2025/03414 , H04L2025/03503 , H04L2025/03509 , H04L2025/03611
摘要： An embodiment of the present invention is related to an analog-to-digital converter comprising a polyphase combiner comprising at least a first combiner filter and a second combiner filter for receiving a plurality of inputs and generating a combined signal. The analog-to-digital converter also comprises a multistage decimator structure for receiving the combined signal and generating a digital sigma-delta output, the multistage decimator structure comprising at least a first decimator comprising a first integrator filter; a first downsampling block and a first differentiator; and a second decimator comprising a second integrator filter; a second downsampling block and a second differentiator.
摘要翻译：本发明的一个实施例涉及包括多相组合器的模数转换器，该多相组合器至少包括第一组合器滤波器和用于接收多个输入并产生组合信号的第二组合器滤波器。所述模数转换器还包括用于接收所述组合信号并产生数字Σ-Δ输出的多级抽取器结构，所述多级抽取器结构包括至少第一抽取器，所述第一抽取器包括第一积分器滤波器; 第一下采样块和第一微分器; 以及第二抽取器，包括第二积分器滤波器; 第二下采样块和第二微分器。

5. 发明授权

US06643675B2 Filtering method and filter 失效
标题翻译：过滤方法和过滤器
公开(公告)号：US06643675B2
公开(公告)日：2003-11-04
申请号：US10187443
申请日：2002-07-02
申请人： Olli Piirainen
发明人： Olli Piirainen
IPC分类号： G06F1717
CPC分类号： H03H17/0288 , H03H17/0671
摘要： The invention relates to a filtering method and a filter implementing the filtering method. In the solution, a signal is filtered by at least one real FIR filter having at least one stop frequency pair whose different frequencies are symmetrically on different sides of at least one alias frequency.
摘要翻译：本发明涉及一种实现滤波方法的滤波方法和滤波器。在该解决方案中，信号被至少一个具有至少一个停止频率对的实际FIR滤波器滤波，其中不同频率对称地在至少一个别名频率的不同侧上。

6. 发明授权

US06624765B2 Apparatus and method for sampling rate conversion 失效
公开(公告)号：US06624765B2
公开(公告)日：2003-09-23
申请号：US10061700
申请日：2002-02-01
申请人： Markus Freidhof , Kurt Schmidt
发明人： Markus Freidhof , Kurt Schmidt
IPC分类号： H03M700
CPC分类号： H03H17/0288 , H03H17/0671 , H03M7/00
摘要： A resampler converts a digital input sequence with an input sampling into a digital output signal sequence with an output sampling rate. An estimation device estimates the sampling rate ratio between the input sampling rate and the output sampling rate and the desired phase of the output signal sequence in an observation interval with a predetermined length of N samples of the output signal sequence, the observation intervals overlapping in the ratio 1:6. A control device compares the actual phase of the output signal sequence with the desired phase and, in a manner dependent on the estimated sampling rate ratio and the deviation of the actual phase from the desired phase, generates a control signal for in each case N/6 samples of the output signal sequence. An interpolator interpolates the input signal sequence for the purpose of generating the output signal sequence at sampling instants whose temporal position is predetermined by a control signal.

7. 发明申请

US20030020551A1 Electric filter with blocking behavior for a predetermined rejection frequency 审中-公开
标题翻译：具有预定拒绝频率的阻塞行为的电动过滤器
公开(公告)号：US20030020551A1
公开(公告)日：2003-01-30
申请号：US10187401
申请日：2002-06-28
申请人： STMicroelectronics GmbH
发明人： Johann Henkel
IPC分类号： H03L007/00
CPC分类号： H03H17/025 , H03H17/0288
摘要： An electric low-pass filter with blocking behavior for a predetermined rejection frequency, comprising a series connection including a FIR filter and an IIR filter, with the parameters of the FIR filter being matched in essence with respect to the blocking behavior at the rejection frequency and the parameters of the IIR filter being matched in essence with respect to the low-pass behavior. It is possible with such a filter to obtain good low-pass behavior with very high attenuation of the frequency to be rejected, with relatively low circuit expenditure and high stability with respect to oscillation tendency.
摘要翻译：一种具有预定抑制频率的阻塞行为的电低通滤波器，包括包括FIR滤波器和IIR滤波器的串联连接，FIR滤波器的参数本质上与拒绝频率处的阻塞行为相匹配;以及 IIR滤波器的参数本质上与低通行为相匹配。这种滤波器可以获得良好的低通行为，具有非常高的被拒绝频率的衰减，具有相对低的电路消耗和相对于振荡趋势的高稳定性。

8. 发明申请

US20020109617A1 Device and method for sampling rate conversion 失效
标题翻译：采样率转换的设备和方法
公开(公告)号：US20020109617A1
公开(公告)日：2002-08-15
申请号：US10072894
申请日：2002-02-12
发明人： Markus Freidhof
IPC分类号： H03M007/00
CPC分类号： H03H17/0288 , H03H17/0422 , H03H17/0628 , H03H17/0671 , H03M7/00
摘要： A resampler device and method are used to convert a digital input signal string (Sin) with an input-sampling rate into a digital output signal string (Sout) with a higher output-sampling rate. Prior to interpolation, a time shift (tmod(n)/Tout) is first determined for every sampling time (tnulln) of the output signal string (sout) relative to a next sampling time (tinull1) of the input signal string (sin). Then the time shift (nullt(n)/Tout) of the sampling time (tnulln) of the output signal string (Sout) relative to the preceding sampling time (ti) of the input signal string (Sin) is determined from the previously determined time shift (tmod(n)/Tout) relative to the next sampling time (tinull1).
摘要翻译：使用重采样器件和方法将具有输入采样率的数字输入信号串（Sin）转换成具有较高输出采样速率的数字输出信号串（Sout）。在插值之前，首先针对输入信号串（sout）相对于输入信号的下一个采样时间（ti + 1）的每个采样时间（t'n）确定时移（tmod（n）/ Tout）字符串（sin）。然后，根据输入信号串（Sout）的输入信号串（Sout）的采样时间（t'n）相对于输入信号串（Sin）的先前采样时间（ti）的时间偏移（DELTAt（n）/ Tout）相对于下一个采样时间（ti + 1）的预先确定的时移（tmod（n）/ Tout）。

9. 发明申请

US20020105448A1 Device and method for conversion of sampling rate 失效
标题翻译：用于转换采样率的装置和方法
公开(公告)号：US20020105448A1
公开(公告)日：2002-08-08
申请号：US10062134
申请日：2002-02-01
发明人： Markus Freidhof
IPC分类号： H03M007/00
CPC分类号： H03H17/0288 , H03H17/0628 , H03H17/0671
摘要： A resampler is used to convert an input digital signal sequence having an input sampling rate into an output digital signal sequence having an output sampling rate (fout). An estimating unit estimates the sampling rate ratio between the input sampling rate and the output sampling rate (fout) and estimates the set point phase of the output signal sequence in observation intervals whose observation length is variable. A controlling system compares the actual phase of the output signal sequence with the set point phase and generates a control signal (RTC,k) as a function of the estimated sampling rate ratio and the deviation of the actual phase from the set point phase. An interpolator interpolates the input signal sequence for generating the output signal sequence at sampling times whose location in time is predetermined by the control signal (RTC,k).
摘要翻译：重采样器用于将具有输入采样率的输入数字信号序列转换成具有输出采样率（fout）的输出数字信号序列。估计单元估计输入采样率和输出采样率（fout）之间的采样率比，并估计观测长度可变的观测间隔中输出信号序列的设定点相位。控制系统将输出信号序列的实际相位与设定点相位进行比较，并根据估计的采样率比和实际相位与设定值相位的偏差产生控制信号（RTC，k）。内插器插值输入信号序列，用于通过控制信号（RTC，k）预先确定其时间位置的采样时间产生输出信号序列。

10. 发明申请

US20020093437A1 Device and method for sampling rate conversion 失效
标题翻译：采样率转换的设备和方法
公开(公告)号：US20020093437A1
公开(公告)日：2002-07-18
申请号：US10045161
申请日：2002-01-15
发明人： Markus Freidhof , Kurt Schmidt
IPC分类号： H03M007/00
CPC分类号： H03H17/0288 , H03H17/0671
摘要： A resampler (1) is used to convert a digital input signal string (Sin) with an input sampling rate (fin) into a digital output signal string (Sout) with an output sampling rate (fout). An estimating unit (11) estimates a sampling rate ratio (Rk) between the input sampling rate (fin) and the output sampling rate (fout) and a setpoint phase of the output signal string (Sout). A regulating unit (12) compares an actual phase of the output signal string (Sout) to the setpoint phase, and generates a control signal (RTC,k) as a function of the estimated sampling rate ratio (Rk) and a deviation of the actual phase from the setpoint phase. An interpolator (7) interpolates the input signal string (Sin) for producing the output signal string (Sout) at sampling times whose temporal position is determined by the control signal (RTC,k).
摘要翻译：重采样器（1）用于以输入采样率（fout）将具有输入采样率（fin）的数字输入信号串（Sin）转换成数字输出信号串（Sout）。估计单元（11）估计输入采样率（fin）和输出采样率（fout）之间的采样率比（Rk）和输出信号串（Sout）的设定点相位。调节单元（12）将输出信号串（Sout）的实际相位与设定点相比较，并且产生作为估计采样率（Rk）的函数的控制信号（RTC，k）和设定相位的实际相位。在由时间位置由控制信号（RTC，k）确定的采样时刻，内插器（7）内插用于产生输出信号串（Sout）的输入信号串（Sin）。

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