专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US3296507A Rugged microwave tunnel diode having a fine mesh screen as one electrode supported by two cementitious bodies 失效
标题翻译：坚固的微波隧道二极管，具有细网孔作为由两个水泥体支撑的一个电极
公开(公告)号：US3296507A
公开(公告)日：1967-01-03
申请号：US44650365
申请日：1965-04-08
申请人： PHILCO CORP
发明人： MITCHELL DAVIS , GOLDMAN RICHARD L , SIRVYDAS VICTOR C
IPC分类号： H01L23/488 , H01L29/00
CPC分类号： H01L23/488 , H01L24/37 , H01L24/40 , H01L24/63 , H01L29/00 , H01L2224/13078 , H01L2224/1319 , H01L2224/37011 , H01L2224/3716 , H01L2224/3754 , H01L2224/40479 , H01L2224/83801

2. 发明授权

US09978676B2 Sub-terahertz/terahertz interconnect 有权
公开(公告)号：US09978676B2
公开(公告)日：2018-05-22
申请号：US15167796
申请日：2016-05-27
申请人： The Regents of the University of California
发明人： Qun Gu , Xiaoguang Liu , Neville C. Luhmann, Jr. , Bo Yu
IPC分类号： H01P1/02 , H01L23/50 , H01P5/08 , H01L23/52 , H01L23/66 , H01P5/107
CPC分类号： H01L23/50 , H01L23/52 , H01L23/66 , H01L24/63 , H01P5/08
摘要： An interconnect is described that comprises an interconnect channel, and two channel couplers coupled to the two ends of the interconnect channel through respective stoppers that provide a gap between the channel couplers and the interconnect channel. Each channel coupler can comprise a coplanar waveguide, a microstrip line, and a patch-antenna based coupler. The interconnect can enable communication between integrated circuits using signal waves having a frequency between 100 GHz and 3 THz.

3. 发明授权

US3363308A Diode contact arrangement 失效
标题翻译：二极管接点布置
公开(公告)号：US3363308A
公开(公告)日：1968-01-16
申请号：US50520265
申请日：1965-09-09
申请人： TEXAS INSTRUMENTS INC
发明人： LUECK ARTHUR M
IPC分类号： H01L21/00 , H01L23/488 , H01L29/00
CPC分类号： H01L23/488 , H01L21/00 , H01L24/37 , H01L24/40 , H01L24/63 , H01L29/00 , H01L2224/37011 , H01L2224/37599 , H01L2224/40479 , H01L2224/83801 , H01L2924/00014 , Y10S438/979 , H01L2224/37099

4. 发明授权

US07977759B2 Fingerprint sensor chip package method and the package structure thereof 有权
标题翻译：指纹传感器芯片封装方法及其封装结构
公开(公告)号：US07977759B2
公开(公告)日：2011-07-12
申请号：US12547767
申请日：2009-08-26
申请人： En-Min Jow
发明人： En-Min Jow
IPC分类号： H01L31/0203 , H01L21/00
CPC分类号： H01L24/63 , G06K9/00006 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2924/01047 , H01L2924/01079 , H01L2924/09701 , H01L2924/1815 , H01L2924/00014 , H01L2924/00
摘要： A fingerprint sensor chip package method and the package structure thereof are disclosed. The invention includes: providing a substrate; arranging a sensor chip on the substrate, with an active surface of the sensor chip facing upward; forming a patterned conductive colloid on the sensor chip, wherein the patterned conductive colloid extends from the periphery of the active surface of the sensor chip along the side wall of the sensor and electrically connects with the circuit layer of the substrate; forming a non-conductive film to cover the sensor chip, the patterned conductive colloid and a portion of the substrate; and forming a conductive film on the non-conductive film. The patterned conductive colloid replaces the conventional bond wires to improve the product yield and to omit the molding process. The conductive film is electrically connected with the grounding point/area on the substrate to dissipate the static charges for protecting the chip.
摘要翻译：公开了一种指纹传感器芯片封装方法及其封装结构。本发明包括：提供基板; 将传感器芯片布置在基板上，传感器芯片的有效表面朝上; 在所述传感器芯片上形成图案化导电胶体，其中所述图案化导电胶体沿着所述传感器的侧壁从所述传感器芯片的有效表面的周边延伸，并与所述衬底的电路层电连接; 形成非导电膜以覆盖传感器芯片，图案化导电胶体和基底的一部分; 并在非导电膜上形成导电膜。图案化的导电胶体代替常规的接合线以提高产品的产率并省略模制过程。导电膜与衬底上的接地点/区域电连接，以消散静电以保护芯片。

5. 发明申请

US20100258891A1 FINGERPRINT SENSOR CHIP PACKAGE METHOD AND THE PACKAGE STRUCTURE THEREOF 有权
标题翻译：指纹传感器芯片包装方法及其包装结构
公开(公告)号：US20100258891A1
公开(公告)日：2010-10-14
申请号：US12547767
申请日：2009-08-26
申请人： EN-MIN JOW
发明人： EN-MIN JOW
IPC分类号： H01L31/0216 , H01L21/50
CPC分类号： H01L24/63 , G06K9/00006 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2924/01047 , H01L2924/01079 , H01L2924/09701 , H01L2924/1815 , H01L2924/00014 , H01L2924/00
摘要： A fingerprint sensor chip package method and the package structure thereof are disclosed. The invention includes: providing a substrate; arranging a sensor chip on the substrate, with an active surface of the sensor chip facing upward; forming a patterned conductive colloid on the sensor chip, wherein the patterned conductive colloid extends from the periphery of the active surface of the sensor chip along the side wall of the sensor and electrically connects with the circuit layer of the substrate; forming a non-conductive film to cover the sensor chip, the patterned conductive colloid and a portion of the substrate; and forming a conductive film on the non-conductive film. The patterned conductive colloid replaces the conventional bond wires to improve the product yield and to omit the molding process. The conductive film is electrically connected with the grounding point/area on the substrate to dissipate the static charges for protecting the chip.
摘要翻译：公开了一种指纹传感器芯片封装方法及其封装结构。本发明包括：提供基板; 将传感器芯片布置在基板上，传感器芯片的有效表面朝上; 在所述传感器芯片上形成图案化导电胶体，其中所述图案化导电胶体沿着所述传感器的侧壁从所述传感器芯片的有效表面的周边延伸，并与所述衬底的电路层电连接; 形成非导电膜以覆盖传感器芯片，图案化导电胶体和基底的一部分; 并在非导电膜上形成导电膜。图案化的导电胶体代替常规的接合线以提高产品的产率并省略模制过程。导电膜与衬底上的接地点/区域电连接，以消散静电以保护芯片。

6. 发明申请

US20100207229A1 NON-PLANAR MICROCIRCUIT STRUCTURE AND METHOD OF FABRICATING SAME 有权
标题翻译：非平面微型结构及其制造方法
公开(公告)号：US20100207229A1
公开(公告)日：2010-08-19
申请号：US12372982
申请日：2009-02-18
申请人： Jeffrey F. DeNatale , Philip A. Stupar , Robert L. Borwick, III
发明人： Jeffrey F. DeNatale , Philip A. Stupar , Robert L. Borwick, III
IPC分类号： H01L29/00 , H05K1/03 , H01L21/00 , H01L21/4763
CPC分类号： H01L23/13 , H01L21/768 , H01L23/5387 , H01L24/63 , H01L27/14601 , H01L27/14625 , H01L27/14643 , H01L27/14683 , H01L27/14685 , H01L29/0657 , H01L2924/14
摘要： A foldable microcircuit is initially a planar semiconductor wafer on which circuitry has been formed. The wafer is segmented into a plurality of tiles, and a plurality of hinge mechanisms are coupled between adjacent pairs of tiles such that the segmented wafer can be folded into a desired non-planar configuration having a high fill-factor and small gaps between tiles. The hinge mechanisms can comprise an organic material deposited on the wafer such that it provides mechanical coupling between adjacent tiles, with metal interconnections between tiles formed directly over the organic hinges, or routed between adjacent tiles via compliant bridges. Alternatively, the interconnection traces between tiles can serve as part or all of a hinge mechanism. The foldable microcircuit can be, for example, a CMOS circuit, with the segmented tiles folded to form, for example, a semi-spherical structure arranged to provide a wide FOV photodetector array.
摘要翻译：可折叠微电路最初是其上形成有电路的平面半导体晶片。晶片被分割成多个瓦片，并且多个铰链机构联接在相邻的瓦片对之间，使得分割的晶片可以折叠成具有高填充因子和瓦片之间的小间隙的期望的非平面构造。铰链机构可以包括沉积在晶片上的有机材料，使得它提供相邻瓦片之间的机械耦合，并且在有机铰链之间直接形成的瓦片之间的金属互连，或者通过柔性桥接件在相邻瓦片之间布线。或者，瓦片之间的互连迹线可以用作铰链机构的一部分或全部。可折叠微电路可以是例如CMOS电路，其中分段瓦片被折叠以形成例如布置成提供宽FOV光电检测器阵列的半球形结构。

7. 发明授权

US09202838B2 Semiconductor device connection 有权
标题翻译：半导体器件连接
公开(公告)号：US09202838B2
公开(公告)日：2015-12-01
申请号：US13127893
申请日：2009-11-19
申请人： Ian Radley
发明人： Ian Radley
IPC分类号： H01L21/50 , H01L27/146 , H01L23/00
CPC分类号： H01L27/14634 , H01L24/32 , H01L24/63 , H01L24/64 , H01L27/14636 , H01L27/1469 , H01L2924/01005 , H01L2924/01006 , H01L2924/01025 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01057 , H01L2924/01077 , H01L2924/01078 , H01L2924/014 , H01L2924/14
摘要： A method of bonding a semiconductor structure to a substrate to effect both a mechanical bond and a selectively patterned conductive bond, comprising the steps of mechanically bonding a semiconductor structure to a substrate by means of a bonding layer; providing gaps in the bonding layer generally corresponding to a desired conductive bond pattern; providing vias though the substrate generally positioned at the gaps in the bonding layer; causing electrically conductive material to contact the semiconductor structure exposed through the vias. A device made in accordance with the method is also described.
摘要翻译：一种将半导体结构接合到基板以实现机械结合和选择性图案化导电接合的方法，包括通过接合层将半导体结构机械地结合到基板的步骤; 在通常对应于期望的导电键合图案的接合层中提供间隙; 提供通孔，其通常位于接合层的间隙处; 导致导电材料接触通过通孔暴露的半导体结构。还描述了根据该方法制造的装置。

8. 发明申请

US20130018434A1 Void-Free Implantable Hermetically Sealed Structures 审中-公开
标题翻译：无孔植入式密封结构
公开(公告)号：US20130018434A1
公开(公告)日：2013-01-17
申请号：US13619055
申请日：2012-09-14
申请人： Mark J. Zdeblick , Benedict James Costello , Jeremy Frank , Marc Jensen , Todd Thompson , Mohammed Z. Islam
发明人： Mark J. Zdeblick , Benedict James Costello , Jeremy Frank , Marc Jensen , Todd Thompson , Mohammed Z. Islam
IPC分类号： A61N1/375 , H01R43/00
CPC分类号： A61N1/05 , H01L21/561 , H01L23/3107 , H01L24/63 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01033 , H01L2924/01044 , H01L2924/01045 , H01L2924/01047 , H01L2924/01049 , H01L2924/01074 , H01L2924/01076 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/1461 , H01L2924/15787 , Y10T29/49117 , H01L2924/00
摘要： An implantable integrated circuit structure comprising a conformal thin-film sealing layer for hermetically sealing circuitry layers is provided. Also disclosed are electrode structures, leads that include the same, implantable pulse generators that include the leads, as well as systems and kits having components thereof, other implantable devices utilizing the structures, and methods of making and using the subject structures.
摘要翻译：提供了一种包括用于密封电路层的保形薄膜密封层的可植入集成电路结构。还公开了电极结构，包括相同的引线，包括引线的可植入脉冲发生器，以及具有其部件的系统和套件，利用该结构的其它可植入装置，以及制造和使用受试结构的方法。

9. 发明申请

US20100016928A1 VOID-FREE IMPLANTABLE HERMETICALLY SEALED STRUCTURES 审中-公开
标题翻译：无密封可塑性密封结构
公开(公告)号：US20100016928A1
公开(公告)日：2010-01-21
申请号：US12296654
申请日：2007-04-12
申请人： Mark J. Zdeblick , Benedict Costello , Jeremy Frank , Marc Jensen , Todd Thompson , Mohammed Z. Islam
发明人： Mark J. Zdeblick , Benedict Costello , Jeremy Frank , Marc Jensen , Todd Thompson , Mohammed Z. Islam
IPC分类号： A61N1/05
CPC分类号： A61N1/05 , H01L21/561 , H01L23/3107 , H01L24/63 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01033 , H01L2924/01044 , H01L2924/01045 , H01L2924/01047 , H01L2924/01049 , H01L2924/01074 , H01L2924/01076 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/1461 , H01L2924/15787 , Y10T29/49117 , H01L2924/00
摘要： An implantable integrated circuit structure comprising a conformal thin-film sealing layer for hermetically sealing circuitry layers is provided. Also disclosed are electrode structures, leads that include the same, implantable pulse generators that include the leads, as well as systems and kits having components thereof, other implantable devices utilizing the structures, and methods of making and using the subject structures.
摘要翻译：提供了一种包括用于密封电路层的保形薄膜密封层的可植入集成电路结构。还公开了电极结构，包括相同的引线，包括引线的可植入脉冲发生器，以及具有其部件的系统和套件，利用该结构的其它可植入装置，以及制造和使用受试结构的方法。

10. 发明申请

US20160351489A1 SUB-TERAHERTZ/TERAHERTZ INTERCONNECT 有权
标题翻译： SUB-TERAHERTZ / TERAHERTZ INTERCONNECT
公开(公告)号：US20160351489A1
公开(公告)日：2016-12-01
申请号：US15167796
申请日：2016-05-27
申请人： The Regents of the University of California
发明人： Qun Gu , Xiaoguang Liu , Neville C. Luhmann, JR. , Bo Yu
IPC分类号： H01L23/50 , H01P5/08
CPC分类号： H01L23/50 , H01L23/52 , H01L23/66 , H01L24/63 , H01P5/08
摘要： An interconnect is described that comprises an interconnect channel, and two channel couplers coupled to the two ends of the interconnect channel through respective stoppers that provide a gap between the channel couplers and the interconnect channel. Each channel coupler can comprise a coplanar waveguide, a microstrip line, and a patch-antenna based coupler. The interconnect can enable communication between integrated circuits using signal waves having a frequency between 100 GHz and 3 THz.
摘要翻译：描述了一种互连，其包括互连通道，以及两个通道耦合器，其通过各自的阻塞器耦合到互连通道的两端，其提供通道耦合器和互连通道之间的间隙。每个通道耦合器可以包括共面波导，微带线和基于贴片天线的耦合器。互连可以使用具有在100GHz和3THz之间的频率的信号波进行集成电路之间的通信。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式