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1. 发明授权

US11908774B2 Semiconductor package including composite molding structure 有权
公开(公告)号：US11908774B2
公开(公告)日：2024-02-20
申请号：US17850504
申请日：2022-06-27
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Heeseok Lee , Yunhyeok Im
IPC分类号： H01L23/48 , H01L23/498 , H01L23/31 , H01L25/10 , H01L23/40
CPC分类号： H01L23/481 , H01L23/3135 , H01L23/498 , H01L25/105 , H01L2023/4087 , H01L2225/1011 , H01L2225/1041
摘要： A semiconductor package includes; a lower semiconductor chip mounted on a lower package substrate, an interposer on the lower package substrate and including an opening, connection terminals spaced apart from and at least partially surrounding the lower semiconductor chip and extending between the lower package substrate and the interposer, a first molding member including a first material and covering at least a portion of a top surface of the lower semiconductor chip and at least portions of edge surfaces of the lower semiconductor chip, wherein the first molding member includes a protrusion that extends upward from the opening to cover at least portions of a top surface of the interposer proximate to the opening, and a second molding member including a second material, at least partially surrounding the first molding member, and covering side surfaces of the first molding member and the connection terminals, wherein the first material has thermal conductivity greater than the second material.

2. 发明授权

US10032740B2 Semiconductor device and manufacturing method thereof 有权
公开(公告)号：US10032740B2
公开(公告)日：2018-07-24
申请号：US15340785
申请日：2016-11-01
申请人： Amkor Technology, Inc.
发明人： Jong Sik Paek , Doo Hyun Park
IPC分类号： H01L23/00 , H01L23/31 , H01L21/56 , H01L25/10 , H01L23/538
CPC分类号： H01L24/17 , H01L21/56 , H01L21/568 , H01L23/3135 , H01L23/5389 , H01L24/13 , H01L24/16 , H01L24/19 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/85 , H01L24/92 , H01L25/105 , H01L2224/0401 , H01L2224/04042 , H01L2224/04105 , H01L2224/12105 , H01L2224/131 , H01L2224/13147 , H01L2224/16225 , H01L2224/32225 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/73267 , H01L2224/81005 , H01L2224/81203 , H01L2224/81815 , H01L2224/85 , H01L2224/92125 , H01L2225/1011 , H01L2225/1023 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2225/107 , H01L2924/00012 , H01L2924/00014 , H01L2924/12042 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/18161 , H01L2924/18162 , H01L2924/19107 , H01L2924/3511 , H01L2924/014 , H01L2924/00
摘要： A semiconductor device and manufacturing method thereof. Various aspects of the disclosure may, for example, comprise forming a back end of line layer on a dummy substrate, completing at least a first portion of an assembly, and removing the dummy substrate.

3. 发明申请

US20180151512A1 STACKED SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
公开(公告)号：US20180151512A1
公开(公告)日：2018-05-31
申请号：US15485530
申请日：2017-04-12
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
发明人： SHIN-PUU JENG , TZU-JUI FANG , HSI-KUEI CHENG , CHIH-KANG HAN , YI-JEN LAI , HSIEN-WEN LIU , YI-JOU LIN
IPC分类号： H01L23/00 , H01L23/373 , H01L23/31 , H01L23/538 , H01L21/48 , H01L21/56 , H01L25/00 , H01L25/10
CPC分类号： H01L23/562 , H01L21/4853 , H01L21/486 , H01L21/563 , H01L21/565 , H01L23/3114 , H01L23/3128 , H01L23/373 , H01L23/5384 , H01L23/5386 , H01L23/5389 , H01L24/13 , H01L25/0655 , H01L25/105 , H01L25/50 , H01L2224/13025 , H01L2225/1011 , H01L2225/1035 , H01L2225/1058 , H01L2924/07025 , H01L2924/3511
摘要： A semiconductor device includes: a first dielectric layer having a first surface; a molding compound disposed on the first surface of the first dielectric layer; a second dielectric layer having a first surface disposed on the molding compound; a via disposed in the molding compound; and a first conductive bump disposed on the via and surrounded by the second dielectric layer; wherein the first dielectric layer and the second dielectric layer are composed of the same material. The filling material has a thickness between the second dielectric layer and the semiconductor die, and the diameter of the hole is inversely proportional to the thickness of the filling material.

4. 发明申请

US20170062372A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20170062372A1
公开(公告)日：2017-03-02
申请号：US15340785
申请日：2016-11-01
申请人： Amkor Technology, Inc.
发明人： Jong Sik Paek , Doo Hyun Park
IPC分类号： H01L23/00 , H01L23/31 , H01L21/56
CPC分类号： H01L24/17 , H01L21/56 , H01L21/568 , H01L23/3135 , H01L23/5389 , H01L24/13 , H01L24/16 , H01L24/19 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/85 , H01L24/92 , H01L25/105 , H01L2224/0401 , H01L2224/04042 , H01L2224/04105 , H01L2224/12105 , H01L2224/131 , H01L2224/13147 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/73267 , H01L2224/81005 , H01L2224/81203 , H01L2224/81815 , H01L2224/85 , H01L2224/92125 , H01L2225/1011 , H01L2225/1023 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2225/107 , H01L2924/00014 , H01L2924/12042 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/18161 , H01L2924/18162 , H01L2924/19107 , H01L2924/3511 , H01L2924/014 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor device and manufacturing method thereof. Various aspects of the disclosure may, for example, comprise forming a back end of line layer on a dummy substrate, completing at least a first portion of an assembly, and removing the dummy substrate.
摘要翻译：半导体器件及其制造方法。本公开的各个方面可以例如包括在虚拟衬底上形成线层的后端，完成组件的至少第一部分，以及去除虚设衬底。

5. 发明申请

US20150221573A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20150221573A1
公开(公告)日：2015-08-06
申请号：US14313724
申请日：2014-06-24
申请人： Amkor Technology, Inc.
发明人： Jong Sik Paek , Doo Hyun Park
IPC分类号： H01L23/31 , H01L23/00 , H01L21/56
CPC分类号： H01L24/17 , H01L21/56 , H01L21/568 , H01L23/3135 , H01L23/5389 , H01L24/13 , H01L24/16 , H01L24/19 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/85 , H01L24/92 , H01L25/105 , H01L2224/0401 , H01L2224/04042 , H01L2224/04105 , H01L2224/12105 , H01L2224/131 , H01L2224/13147 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/73267 , H01L2224/81005 , H01L2224/81203 , H01L2224/81815 , H01L2224/85 , H01L2224/92125 , H01L2225/1011 , H01L2225/1023 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2225/107 , H01L2924/00014 , H01L2924/12042 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/18161 , H01L2924/18162 , H01L2924/19107 , H01L2924/3511 , H01L2924/014 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor device and manufacturing method thereof. Various aspects of the disclosure may, for example, comprise forming a back end of line layer on a dummy substrate, completing at least a first portion of an assembly, and removing the dummy substrate.
摘要翻译：半导体器件及其制造方法。本公开的各个方面可以例如包括在虚拟衬底上形成线层的后端，完成组件的至少第一部分，以及去除虚设衬底。

6. 发明授权

US08012803B2 Vertically stacked pre-packaged integrated circuit chips 有权
标题翻译：垂直堆叠的预先封装的集成电路芯片
公开(公告)号：US08012803B2
公开(公告)日：2011-09-06
申请号：US12891439
申请日：2010-09-27
申请人： Keith Gann , Douglas M. Albert
发明人： Keith Gann , Douglas M. Albert
IPC分类号： H01L21/00
CPC分类号： H01L25/50 , H01L23/49575 , H01L24/48 , H01L25/105 , H01L25/16 , H01L2224/05599 , H01L2224/45099 , H01L2224/48247 , H01L2224/85399 , H01L2225/06551 , H01L2225/1011 , H01L2225/1035 , H01L2225/1058 , H01L2225/1064 , H01L2924/00014 , H01L2924/14 , H01L2924/181 , H01L2924/3011 , Y10T29/49121 , Y10T29/49146 , Y10T29/49171 , H01L2224/45015 , H01L2924/207 , H01L2924/00 , H01L2924/00012
摘要： Prepackaged chips, such a memory chips, are vertically stacked and bonded together with their terminals aligned. The exterior lead frames are removed including that portion which extends into the packaging. The bonding wires are now exposed on the collective lateral surface of the stack. In those areas where no bonding wire was connected to the lead frame, a bare insulative surface is left. A contact layer is disposed on top of the stack and vertical metalizations defined on the stack to connect the ends of the wires to the contact layer and hence to contact pads on the top surface of the contact layer. The vertical metalizations are arranged and configured to connect all commonly shared terminals of the chips, while the control and data input/output signals of each chip are separately connected to metalizations, which are disposed in part on the bare insulative surface.
摘要翻译：这样的存储芯片的预包装芯片被垂直堆叠并且将其端子对准地结合在一起。外部引线框架被移除，包括延伸到包装中的部分。接合线现在暴露在堆叠的集体侧表面上。在没有接合线与引线框架连接的区域，留下裸露的绝缘表面。接触层设置在堆叠的顶部，并且垂直金属化被限定在堆叠上，以将导线的端部连接到接触层，并且因此接触接触层顶表面上的焊盘。垂直金属化被布置和配置为连接芯片的所有共同的共享端子，而每个芯片的控制和数据输入/输出信号分别连接到部分地设置在裸绝缘表面上的金属化。

7. 发明授权

US07863100B2 Integrated circuit packaging system with layered packaging and method of manufacture thereof 有权
标题翻译：具有分层封装的集成电路封装系统及其制造方法
公开(公告)号：US07863100B2
公开(公告)日：2011-01-04
申请号：US12408662
申请日：2009-03-20
申请人： Joungln Yang , Dongjin Jung , DongSam Park
发明人： Joungln Yang , Dongjin Jung , DongSam Park
IPC分类号： H01L21/00 , H01L23/02 , H01R12/16
CPC分类号： H01L23/49816 , H01L23/3128 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/73265 , H01L2225/0651 , H01L2225/1011 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/10253 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/3511 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method of manufacture of an integrated circuit packaging system includes: forming a base package having a base interposer; forming an intermediate package having an intermediate interposer and an intermediate package embedded link trace, the intermediate package embedded link trace being encapsulated in an intermediate package mold compound; forming a cap package having a cap interposer; and connecting the intermediate package to the cap package and the base package using the intermediate package embedded link trace.
摘要翻译：一种集成电路封装系统的制造方法，包括：形成具有基底插入件的基底封装; 形成具有中间插入件和中间封装嵌入链节迹线的中间封装，所述中间封装嵌入链节迹线封装在中间封装模具化合物中; 形成具有盖插入件的盖封装; 以及使用所述中间封装的嵌入式链路迹线将所述中间封装连接到所述封装封装和所述基底封装。

8. 发明申请

US20100237482A1 INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LAYERED PACKAGING AND METHOD OF MANUFACTURE THEREOF 有权
标题翻译：具有层状包装的集成电路包装系统及其制造方法
公开(公告)号：US20100237482A1
公开(公告)日：2010-09-23
申请号：US12408662
申请日：2009-03-20
申请人： JoungIn Yang , Dongjin Jung , DongSam Park
发明人： JoungIn Yang , Dongjin Jung , DongSam Park
IPC分类号： H01L23/52 , H01L21/98
CPC分类号： H01L23/49816 , H01L23/3128 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/73265 , H01L2225/0651 , H01L2225/1011 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/10253 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/3511 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method of manufacture of an integrated circuit packaging system includes: forming a base package having a base interposer; forming an intermediate package having an intermediate interposer and an intermediate package embedded link trace, the intermediate package embedded link trace being encapsulated in an intermediate package mold compound; forming a cap package having a cap interposer; and connecting the intermediate package to the cap package and the base package using the intermediate package embedded link trace.
摘要翻译：一种集成电路封装系统的制造方法，包括：形成具有基底插入件的基底封装; 形成具有中间插入件和中间封装嵌入链节迹线的中间封装，所述中间封装嵌入链节迹线封装在中间封装模具化合物中; 形成具有盖插入件的盖封装; 以及使用所述中间封装的嵌入式链路迹线将所述中间封装连接到所述封装封装和所述基底封装。

9. 发明授权

US06774473B1 Semiconductor chip module 有权
公开(公告)号：US06774473B1
公开(公告)日：2004-08-10
申请号：US09407204
申请日：1999-09-28
申请人： Ming-Tung Shen
发明人： Ming-Tung Shen
IPC分类号： H01L2302
CPC分类号： H01L24/32 , H01L24/73 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/73215 , H01L2224/73253 , H01L2224/73265 , H01L2225/06517 , H01L2225/1011 , H01L2225/1029 , H01L2225/1052 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/0105 , H01L2924/01078 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/1532 , H01L2924/15331 , H01L2924/00 , H01L2924/00012 , H01L2224/0401
摘要： A semiconductor chip module includes a chip-mounting member having opposite first and second surfaces, a set of circuit traces, and a plurality of plated through holes that extend through the first and second surfaces and that are connected to the circuit traces. A dielectric tape member bonds adhesively a semiconductor chip on the chip-mounting member. A first conductor unit connects electrically contact pads on a pad mounting surface of the semiconductor chip and the circuit traces. A plurality of solder balls are disposed on one of the first and second surfaces of the chip-mounting member, are aligned with and are connected to the plated through holes in the chip-mounting member, respectively.

10. 发明授权

US6072234A Stack of equal layer neo-chips containing encapsulated IC chips of different sizes 有权
标题翻译：堆叠的包含不同尺寸的封装的IC芯片的等层新型芯片
公开(公告)号：US6072234A
公开(公告)日：2000-06-06
申请号：US316740
申请日：1999-05-21
申请人： Andrew N. Camien , James S. Yamaguchi
发明人： Andrew N. Camien , James S. Yamaguchi
IPC分类号： H01L23/29 , H01L25/10 , H01L23/02
CPC分类号： H01L24/96 , H01L23/293 , H01L24/97 , H01L25/10 , H01L25/105 , H01L25/16 , H01L2224/04105 , H01L2224/20 , H01L2225/1011 , H01L2924/01005 , H01L2924/01013 , H01L2924/01033 , H01L2924/01075 , H01L2924/01078 , H01L2924/01082 , H01L2924/10253 , H01L2924/14 , H01L2924/3511
摘要： Neo-chips suitable for stacking in 3D multi-layer electronic modules are formed by embedding (encapsulating ) IC chips in epoxy material which provides sufficient layer rigidity after curing. The encapsulated chips are formed by placing separate IC chips, usually "known good" die, in a neo-wafer, which is subjected to certain process steps, and then diced to form neo-chips. The following benefits are obtained: (1) The starting IC chips (die) intended for stacking may have different sizes, and serve different electronic purposes. After they are encapsulated in same-size neo-chips, they can be efficiently stacked using well-developed processing steps; (2) The individual chips for stacking can be purchased as "known good" die. This means than an essentially unlimited choice of die is available to the stacking entity, and that the die are pretested when they are ready for stacking; (3) A given layer can contain a plurality of individual die; and (4) The die encapsulating material is dielectric, so that no special steps are required to prepare the access plane of the stack for metalization. Heretofore, this preparation of the access plane has required either the etch-back plus passivation process, or the passivation plus trench-formation process.
摘要翻译：适用于3D多层电子模块堆叠的新芯片通过将环氧树脂材料嵌入（封装）IC芯片形成，其在固化后提供足够的层刚度。封装的芯片通过将单独的IC芯片（通常是“已知的”）芯片放置在经受一定工艺步骤的新晶片中，然后切割形成新芯片来形成。获得以下好处：（1）用于堆叠的起始IC芯片（芯片）可能具有不同的尺寸，并且用于不同的电子目的。在封装相同尺寸的新芯片之后，可以使用发达的加工步骤有效地堆叠; （2）堆叠的各个芯片可以作为“已知的”模具购买。这意味着比堆叠实体可用的基本上无限制的模具选择，并且当它们准备堆叠时，模具被预先测试; （3）给定的层可以包含多个单独的模具; 和（4）芯片封装材料是电介质的，因此不需要特殊的步骤来制备用于金属化的叠层的存取平面。到目前为止，存取平面的这种制备需要回蚀加钝化处理或钝化加沟槽形成工艺。

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