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1. 发明申请

US20140163907A1 SYSTEMS AND METHODS FOR FAULT DETECTION 审中-公开
标题翻译：用于故障检测的系统和方法
公开(公告)号：US20140163907A1
公开(公告)日：2014-06-12
申请号：US13709928
申请日：2012-12-10
申请人： GENERAL ELECTRIC COMPANY
发明人： Daniel Milton Alley , Michael G. Wise , Alan Mathason , Fred Henry Boettner , Stephen Emerson Douthit , Richard Reed
IPC分类号： G01R31/00 , G06F15/00
CPC分类号： G01R31/00 , G05B9/02 , G05B9/03 , G06F11/1608 , G06F11/1625 , G06F11/186 , G06F11/188 , G06F15/00 , G06F2201/81
摘要： Systems, methods, and computer-readable media for fault detection are disclosed. At least one controller may identify a plurality of values where each value corresponds to a monitored parameter or a measured parameter. The at least one controller may determine a respective deviation between each of the plurality of values and an expected value, and may further determine whether at least one of the respective deviations exceeds a threshold. Upon a determination that at least one of the respective deviations exceeds the threshold, a fault may be detected. Each of the plurality of values may be associated with a respective device that monitors or measures the value. A detected fault may be associated with the device that monitors or measures the value determined to deviate from the expected value by more than the threshold.
摘要翻译：公开了用于故障检测的系统，方法和计算机可读介质。至少一个控制器可以标识多个值，其中每个值对应于被监视的参数或测量的参数。所述至少一个控制器可以确定所述多个值中的每一个与预期值之间的相应偏差，并且还可以确定各个偏差中的至少一个是否超过阈值。在确定各个偏差中的至少一个超过阈值时，可以检测到故障。多个值中的每一个可以与监视或测量该值的相应设备相关联。检测到的故障可以与监视或测量所确定的偏离预期值大于阈值的设备相关联。

2. 发明授权

US08499189B2 Unified, workload-optimized, adaptive RAS for hybrid systems 有权
标题翻译：用于混合系统的统一的，工作负载优化的自适应RAS
公开(公告)号：US08499189B2
公开(公告)日：2013-07-30
申请号：US13708931
申请日：2012-12-08
申请人： International Business Machines Corporation
发明人： Rajaram B. Krishnamurthy , Carl J. Parris , Donald W. Schmidt , Benjamin P. Segal
IPC分类号： G06F11/00
CPC分类号： G06F9/50 , G06F11/008 , G06F11/1645 , G06F11/188
摘要： A method, system, and computer program product for maintaining reliability in a computer system. In an example embodiment, the method includes performing a first data computation by a first set of processors, the first set of processors having a first computer processor architecture. The method continues by performing a second data computation by a second processor coupled to the first set of processors, the second processor having a second computer processor architecture, the first computer processor architecture being different than the second computer processor architecture. Finally, the method includes dynamically allocating computational resources of the first set of processors and the second processor based on at least one metric while the first set of processors and the second processor are in operation such that the accuracy and processing speed of the first data computation and the second data computation are optimized.
摘要翻译：一种用于在计算机系统中维持可靠性的方法，系统和计算机程序产品。在示例实施例中，该方法包括由第一组处理器执行第一数据计算，第一组处理器具有第一计算机处理器架构。该方法通过由耦合到第一组处理器的第二处理器执行第二数据计算而继续，第二处理器具有第二计算机处理器架构，第一计算机处理器架构不同于第二计算机处理器架构。最后，该方法包括在第一组处理器和第二处理器运行时基于至少一个度量来动态分配第一组处理器和第二处理器的计算资源，使得第一数据计算的精度和处理速度并且第二数据计算被优化。

3. 发明授权

US07800412B2 Fault detection and isolation of redundant signals 失效
标题翻译：故障检测和隔离冗余信号
公开(公告)号：US07800412B2
公开(公告)日：2010-09-21
申请号：US12029642
申请日：2008-02-12
申请人： Kevin E. Dutton
发明人： Kevin E. Dutton
IPC分类号： H03K5/22 , G06F11/00
CPC分类号： G06F11/188 , G06F11/183 , G06F11/184
摘要： A method of detecting signal faults comprises sampling at least three redundant signals; calculating a difference signal for each unique pair-wise comparison of the at least three sampled redundant signals; comparing each difference signal to an expected distribution for the difference signals; and determining if one of the at least three redundant signals is faulty based on the comparison of each difference signal to the expected distribution.
摘要翻译：检测信号故障的方法包括对至少三个冗余信号进行采样; 为所述至少三个采样的冗余信号的每个唯一的成对比较计算差分信号; 将每个差分信号与差分信号的预期分布进行比较; 以及基于每个差分信号与所述预期分布的比较来确定所述至少三个冗余信号中的一个是否有故障。

4. 发明申请

US20100023799A1 DETERMINING CORRECTNESS OF JOB PLANS IN A STREAM PROCESSING APPLICATION 失效
标题翻译：确定流程处理应用中作业计划的正确性
公开(公告)号：US20100023799A1
公开(公告)日：2010-01-28
申请号：US12180615
申请日：2008-07-28
申请人： Zachary A. Garbow
发明人： Zachary A. Garbow
IPC分类号： G06F11/00
CPC分类号： G06F11/1637 , G06F11/1691 , G06F11/184 , G06F11/188
摘要： Embodiments of the invention provide techniques for determining the correctness of similar job plan segments in a stream processing application. In one embodiment, a job manager may be configured to identify similar job plan segments based on data formats, functionality, and surrounding processing elements. The job manager plan may be further configured to determine whether the similar segments provide inconsistent results, and if so, to determine which of the inconsistent similar segments is invalid. The job manager may identify an invalid processing element included in the invalid segment. The job manager may also perform corrective actions to address the invalid processing element.
摘要翻译：本发明的实施例提供了用于确定流处理应用中类似作业计划段的正确性的技术。在一个实施例中，作业管理器可以被配置为基于数据格式，功能和周围的处理元件来识别类似的作业计划段。作业管理器计划可以被进一步配置以确定类似段是否提供不一致的结果，如果是，则确定哪些不一致的相似段是无效的。作业管理器可以识别无效段中包括的无效处理元素。作业管理器还可以执行纠正措施来解决无效处理元件。

5. 发明授权

US06567927B1 Logic unit operable under the byzantine algorithm, computer unit having such logic unit, composite assembly comprised of logic units or computer units, and method of operating such an assembly 有权
标题翻译：在拜占庭算法下运行的逻辑单元，具有这种逻辑单元的计算机单元，由逻辑单元或计算机单元组成的复合组件，以及操作这种组件的方法
公开(公告)号：US06567927B1
公开(公告)日：2003-05-20
申请号：US09565139
申请日：2000-05-05
申请人： Volker Brinkmann
发明人： Volker Brinkmann
IPC分类号： G06F1100
CPC分类号： G06F11/188 , G06F11/181 , G06F11/182
摘要： A logic unit operable under the Byzantine algorithm for the architectural configuration of a composite assembly which tolerates an amount of F errors in simultaneous manner as to time and a plurality of inputs for in-reading of data into registers of a set of registers, and a plurality of outputs for out-reading of data from the registers, whereby each output is connectable with an input of a further logic unit, whereby the registers are coupled with the inputs and outputs in such a manner that each register is capable of being read-in and being capable of being read-out independently of the position of the logic unit within the assembly, by means of a position invariant, relative identification, as well as a computer unit with such a logic unit, as well as the fault-tolerant assembly of such logic/computer units, and a method of operating a fault tolerant assembly.
摘要翻译：一种逻辑单元，可在拜占庭算法下运行，用于复合组件的体系结构配置，该组合组件允许同时以时间为单位的F错误量，以及用于将数据读入一组寄存器的寄存器的多个输入，以及多个输出用于从寄存器中读出数据，由此每个输出可与另一个逻辑单元的输入端连接，由此寄存器与输入和输出耦合，使得每个寄存器能够被读取，并且能够通过位置不变，相对标识以及具有这种逻辑单元的计算机单元独立于组件内的逻辑单元的位置被读出，以及容错这种逻辑/计算机单元的组装以及操作容错组件的方法。

6. 发明授权

US6038683A Replicated controller and fault recovery method thereof 失效
标题翻译：复制控制器及其故障恢复方法
公开(公告)号：US6038683A
公开(公告)日：2000-03-14
申请号：US40146
申请日：1998-03-17
申请人： Kotaro Shimamura , Yuuichiro Morita , Yoshitaka Takahashi , Takashi Hotta , Hiroyasu Satou , Shigeta Ueda , Akira Bando , Hirokazu Suzuki , Koji Sakamoto
发明人： Kotaro Shimamura , Yuuichiro Morita , Yoshitaka Takahashi , Takashi Hotta , Hiroyasu Satou , Shigeta Ueda , Akira Bando , Hirokazu Suzuki , Koji Sakamoto
IPC分类号： G05B9/03 , G06F11/18 , H02M7/48 , G06F11/00
CPC分类号： G06F11/182 , G05B9/03 , G06F11/184 , G06F11/188 , Y10S707/99953
摘要： A replicated controller and a fault recovery method therefor which can restore a faulty system to a normal state without interrupting operation of an equipment, even in an equipment controller performing processing with short operating periods.In a fault recovery method for a replicated controller, control data is divided into a plurality of blocks on the basis of dependency of the blocks, and a plurality of blocks are transferred in a sequential order of superiority of the dependency from the normally operating system to the faulty system in a period over a plurality of operating periods. BY this, even in an equipment controller performing processing at a short operating period, the system, in which failure is caused, can be restored into normal state without interrupting operation of the equipment.
摘要翻译：复制控制器及其故障恢复方法，即使在执行短操作周期的处理的设备控制器中，也可以将故障系统恢复到正常状态而不中断设备的操作。在复制控制器的故障恢复方法中，基于块的依赖性将控制数据划分为多个块，并且以从依赖关系的正常操作系统的优越性的顺序传送多个块在多个操作期间内的故障系统。由此，即使是在短时间内进行处理的设备控制器中，也可以在不中断设备的运转的情况下将导致故障的系统恢复到正常状态。

7. 发明授权

US06035416A Method and apparatus for interface dual modular redundancy 失效
标题翻译：接口双模块冗余的方法和装置
公开(公告)号：US06035416A
公开(公告)日：2000-03-07
申请号：US950474
申请日：1997-10-15
申请人： George Michel Abdelnour , Arthur Latimer Bond , Robert W. Downes , Kenneth H. Potter, Jr. , Frederick K. Yu
发明人： George Michel Abdelnour , Arthur Latimer Bond , Robert W. Downes , Kenneth H. Potter, Jr. , Frederick K. Yu
IPC分类号： G06F11/00 , G06F11/16 , G06F11/18 , G06F11/20 , G06F11/30
CPC分类号： G06F11/182 , G06F11/0757 , G06F11/076 , G06F11/187 , G06F11/188 , G06F11/2017 , G06F11/0763
摘要： Controller triple modular redundancy is substantially achieved and reliability improved in a system having duplicate controllers that serve peripheral units. Both controllers detect suspected faults in itself and in the other controller. A peripheral unit that suspects a faulty active controller requests a switch of the active controller. A voting circuit processes votes from the controllers and the active controller switch signal from the peripheral units to select the active controller. The signaling paths between the controllers used to convey votes and active controller information are duplicated. The signals on these signaling paths convey information by using oscillating signals of different frequencies.
摘要翻译：在具有服务于外围单元的重复控制器的系统的系统中，实质上实现了控制器三重模块化冗余并提高两个控制器本身和另一个控制器中检测到疑似故障。怀疑主动控制器故障的外设单元请求主动控制器的切换。投票电路处理来自控制器的投票和来自外围设备的主动控制器切换信号以选择主动控制器。用于传送投票和主动控制器信息的控制器之间的信令路径被重复。这些信令路径上的信号通过使用不同频率的振荡信号传送信息。

8. 发明授权

US5751726A Representative value selector and an embodying method therefor 失效
标题翻译：代表值选择器及其体现方法
公开(公告)号：US5751726A
公开(公告)日：1998-05-12
申请号：US513060
申请日：1995-08-09
申请人： You Taeq Kim
发明人： You Taeq Kim
IPC分类号： G06F11/18 , G06F11/00
CPC分类号： G06F11/188 , G06F11/183
摘要： Disclosed is an operating device which includes an algorithm for selecting one representative value among various calculated results based on diverse interpretations with respect to identical events or same information, and a method for selecting the representative value among several values, in which a separate circuit is not constructed for calculating input data values, but a program is inherently incorporated into an existing operational device for selecting the input data values, thereby avoiding an unnecessary circuit construction while a method for searching out most frequently distributed data values is introduced by processing data values included in a certain error range as the same value to solve a problem in the Triple Modular Redundance system, and reduce cost required for constructing the circuitry.
摘要翻译：公开了一种操作装置，其包括用于基于对相同事件或相同信息的多种解释来在各种计算结果中选择一个代表值的算法，以及用于在多个值中选择代表值的方法，其中单独的电路不是被构造成用于计算输入数据值，但是程序固有地并入到用于选择输入数据值的现有操作装置中，从而避免了不必要的电路构造，同时通过处理包含在数据中的数据值来引入用于搜索最频繁分布的数据值的方法一定的误差范围作为相同的值来解决三重模块化冗余系统中的问题，并降低构建电路所需的成本。

9. 发明授权

US5666483A Redundant processing system architecture 失效
标题翻译：冗余处理系统架构
公开(公告)号：US5666483A
公开(公告)日：1997-09-09
申请号：US532949
申请日：1995-09-22
申请人： Charles R. McClary
发明人： Charles R. McClary
IPC分类号： G01P9/00 , G01C19/00 , G01C19/66 , G01P15/18 , G06F11/18 , G06F11/00
CPC分类号： G06F11/183 , G06F11/1675 , G06F11/188
摘要： Disclosed is a fault-tolerant and/or fail-safe information processing system architecture for handling information from a plurality of independent subsystems which provide information related to selected input quantities, and which includes a plurality of redundant information processors for deriving specific processor output data as a function of the selected subsystem input quantities.
摘要翻译：公开了一种用于处理来自多个独立子系统的信息的容错和/或故障安全信息处理系统架构，其提供与所选择的输入量相关的信息，并且包括多个冗余信息处理器，用于将特定处理器输出数据导出为所选子系统输入量的函数。

10. 发明授权

US4868826A Fault-tolerant output circuits 失效
标题翻译：容错输出电路
公开(公告)号：US4868826A
公开(公告)日：1989-09-19
申请号：US91086
申请日：1987-08-31
申请人： Steven E. Smith , Janusz M. Kucharski , Kenneth J. Murphy
发明人： Steven E. Smith , Janusz M. Kucharski , Kenneth J. Murphy
IPC分类号： G05B9/03 , G06F11/00 , G06F11/16 , G06F11/18 , G06F11/20 , G06F11/267
CPC分类号： G06F11/188 , G05B9/03 , G06F11/0796 , G06F11/18 , G06F11/20 , G06F11/0757 , G06F11/1608 , G06F11/202 , G06F11/2215
摘要： Circuit modules for providing digital or analog outputs from computational devices in such a manner that the components of the output circuit modules are tolerant of malfunctions in one or more of the components. In the digital output embodiment of the invention, output signals are independently derived using two voting circuits and are then applied to two switches connected in series to provide a fail-safe condition for most types of failure of the switches or the voting circuits. Two identical modules provide the ability to faithfully follow commanded on or off signals in all but a statistically small number of situations, and permit convenient replacement of a defective module without affecting output through the other module. In an analog output module, two independent voting circuits provide voted digital outputs to separate digital-to-analog converters, the outputs of which are compared to generate a validity signal that is used to control an output switch. The validity signal for the module can be combined logically with the switch status of another identical module, to determine which of the modules should be activated by closure of its output switch. An inactive module can be removed and replaced without affecting the integrity of the analog output signals.
摘要翻译：用于从计算设备提供数字或模拟输出的电路模块，使得输出电路模块的组件能够容忍一个或多个组件中的故障。在本发明的数字输出实施例中，使用两个投票电路独立地导出输出信号，然后将其应用于串联连接的两个开关，为开关或投票电路的大多数类型的故障提供故障安全条件。两个相同的模块提供了在统计学上很少数量的情况下忠实地遵循所指示的开或关信号的能力，并且允许方便地更换有缺陷的模块而不影响通过另一模块的输出。在模拟输出模块中，两个独立的投票电路提供投票数字输出以分离数模转换器，将其输出进行比较以产生用于控制输出开关的有效信号。模块的有效信号可以逻辑地与另一个相同模块的开关状态组合，以确定哪个模块应通过关闭其输出开关来激活。可以移除和更换非活动模块，而不影响模拟输出信号的完整性。

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