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    • 1. 发明授权
    • Oscilloscope based return loss analyzer
    • 基于示波器的回波损耗分析仪
    • US07271575B2
    • 2007-09-18
    • US10637901
    • 2003-08-07
    • John J. PickerdLaudie J. Doubrava
    • John J. PickerdLaudie J. Doubrava
    • G01R23/00G01R23/16G01R27/06
    • G01R13/22
    • A system, apparatus and method for performing differential return loss measurements and other measurements as a function of frequency uses a digital storage oscilloscope (DSO) having spectral analysis functions. A waveform generator generates a differential test signal in the form of a series of pulses where each pulse includes spectral components associated with each of a plurality of frequencies of interest. A test fixture presents the differential test waveform to a load including at least one of a device under test (DUT), a short circuit, an open circuit and a balanced load. A signal acquisition device differentially measures the test waveform during each of the load conditions. The signal acquisition device computes an error correction parameter using measurements made during the short circuit, open circuit and balanced load conditions. The correction parameter tends to offset signal acquisition errors within measurements made during the DUT load condition.
    • 用于执行差分回波损耗测量和作为频率的函数的其他测量的系统,装置和方法使用具有频谱分析功能的数字存储示波器(DSO)。 波形发生器以一系列脉冲的形式产生差分测试信号,其中每个脉冲包括与感兴趣的多个频率中的每一个相关联的频谱分量。 测试夹具将差分测试波形呈现给包括被测器件(DUT),短路,开路和平衡负载中的至少一个的负载。 信号采集装置在每个负载条件下差分地测量测试波形。 信号采集装置使用在短路,开路和平衡负载条件下进行的测量来计算纠错参数。 在DUT负载条件下进行的测量中,校正参数倾向于抵消信号采集误差。
    • 3. 发明授权
    • Method which provides debounced inputs from a touch screen panel by
waiting until each x and y coordinates stop altering
    • 通过等待直到每个x和y坐标停止改变来提供来自触摸屏面板的去抖动输入的方法
    • US5025411A
    • 1991-06-18
    • US939645
    • 1986-12-08
    • James L. TallmanTerry G. Sherbeck
    • James L. TallmanTerry G. Sherbeck
    • G06F3/042G01R13/22G01R13/34G06F3/033G06F3/041G06F3/048
    • G06F3/033G01R13/22G01R13/347
    • A system for providing input to a computer comprises a touchscreen apparatus for generating a grid of horizontal and vertical light beams and producing a set of output signals, each indicating whether a corresponding one of the light beams strikes an object. A scanning device repeatedly scans the states of the output signals, stores data representing the last scanned state of each output signal, and transmits a first interrupt signal to the computer whenever the state of any one of the output signals changes. In response to the interrupt signal, the computer reads the stored scan data, determines whether the data indicates that a horizontal and a vertical light beam is striking an object, and if so, sets parameter values to identify the horizontal and vertical light beams. In response to a second interrupt signal periodically generated by a clock, the computer determines whether or not the parameter values have remained constant for a predetermined period, and if so executes a routine responsive to the parameter values.
    • 用于向计算机提供输入的系统包括用于产生水平和垂直光束的网格并产生一组输出信号的触摸屏设备,每个输出信号指示对应的一个光束是否撞击物体。 扫描装置重复地扫描输出信号的状态,存储表示每个输出信号的最后扫描状态的数据,并且每当输出信号中的任一个的状态改变时,将第一中断信号发送到计算机。 响应于中断信号,计算机读取存储的扫描数据,确定数据是指水平和垂直光束是否被击中物体,如果是,则设置参数值以识别水平和垂直光束。 响应于由时钟周期性地产生的第二中断信号,计算机确定参数值是否在预定时间段内保持不变,并且如果执行响应于参数值的例程。
    • 4. 发明授权
    • Oscilloscope memory control
    • 示波器内存控制
    • US4801851A
    • 1989-01-31
    • US418190
    • 1982-09-14
    • Bernard M. GordonColin Gyles
    • Bernard M. GordonColin Gyles
    • G01R13/22G01R13/34H01J29/70H01J29/76
    • G01R13/22G01R13/34
    • A memory control for use with a digital oscilloscope having a display and a digital memory storing a sequence of signal samples. The sequence of signal samples is cyclically read from memory and displayed. The memory control adjusts the memory access operation to provide a controlled signal flow to the display at a rate within the slew-rate limits of the graphic display. In the memory control, the point slew, or distance over which the display beam moves from the present data point to the next point, is measured. If the point slew relative to the time interval between displayed signal samples exceeds the slew-rate capability of the display, the signal flow from the memory for subsequent data points is reduced or inhibited for a time sufficient to allow the display to reach a coordinate position corresponding to the desired data point.
    • 一种与具有显示器和数字存储器存储信号样本序列的数字示波器一起使用的存储器控​​制。 信号样本的序列从存储器循环读取并显示。 存储器控制调节存储器访问操作,以图形显示的转换速率限制内的速率向显示器提供受控信号流。 在存储器控制中,测量点摆动或显示光束从当前数据点移动到下一点的距离。 如果相对于所显示的信号样本之间的时间间隔相对于点的转速超过显示器的转换速率能力,则来自用于后续数据点的存储器的信号流被减少或抑制足以允许显示器到达坐标位置的时间 对应于所需的数据点。
    • 6. 发明授权
    • Digital waveform processing oscilloscope with distributed data multiple
plane display system
    • 数字波形处理示波器具有分布式数据多平面显示系统
    • US4634970A
    • 1987-01-06
    • US567055
    • 1983-12-30
    • Randall K. PayneRussell H. Nord
    • Randall K. PayneRussell H. Nord
    • G01R13/22G01R13/34
    • G01R13/34G01R13/22
    • A raster display digital oscilloscope includes an analog to digital converter and a memory array for developing and storing a digital measurement signal amplitude-dependent on an acquired input signal. After processing stored digital signals are conveyed to an output circuit which includes a raster-scanned CRT and three display memory planes independently addressable by the CPU for receiving in discrete address locations the digital data. Corresponding address locations in the three planes are read in synchronism with the CRT scan to develop a display signal for application to the CRT to produce a display corresponding to the sum of the data stored in the three planes. The digital signals are automatically spread out or bunched up within the display planes to compensate for differences between the data acquisition rate and the scan rate.
    • 光栅显示数字示波器包括模数转换器和存储器阵列,用于开发和存储取决于获取的输入信号的数字测量信号。 在处理存储的数字信号之后,传送到包括光栅扫描CRT和三个显示存储器平面的输出电路,该三个显示存储器平面可由CPU单独寻址,以便在离散地址位置接收数字数据。 与CRT扫描同步地读取三个平面中的对应地址位置,以开发用于CRT的显示信号,以产生对应于存储在三个平面中的数据之和的显示。 数字信号在显示平面内自动展开或聚集,以补偿数据采集率和扫描速率之间的差异。
    • 7. 发明授权
    • Cathode ray tube display device
    • 阴极射线管显示装置
    • US4547709A
    • 1985-10-15
    • US335365
    • 1981-12-29
    • Jack G. French
    • Jack G. French
    • G01S7/06G01R13/22G01S7/12G09G1/04H01J29/76H01J29/78
    • H01J29/76G01R13/22G01S7/12
    • A cathode ray tube display device having beam deflection coils (8,10,12,14) and means (44 and 46) for applying to inductive means (58 plus the coils) which includes the beam deflection coils a voltage for causing a ramp current to flow in the coils to produce progressive beam deflection, comprising means (52,54,56) for selectively modifying interconnections between the coils to change the inductance presented to the voltage applying means and thus change the gradient of the ramp current and the rate of beam deflection, said interconnection modifying means being operable to change the number of deflection coils through which said current flows.
    • 一种具有光束偏转线圈(8,10,12,14)和用于施加到电感装置(58加上线圈)的装置(44和46)的阴极射线管显示装置,其包括光束偏转线圈,用于产生斜坡电流 在线圈中流动以产生渐进的光束偏转,包括用于选择性地修改线圈之间的互连的装置(52,54,56),以改变呈现给电压施加装置的电感,并因此改变斜坡电流的梯度和 所述互连修改装置可操作以改变所述电流流过的偏转线圈的数量。
    • 10. 发明授权
    • Composite logic analyzer capable of data display in two time-related
formats
    • 能够以两种时间相关格式显示数据的复合逻辑分析仪
    • US4364036A
    • 1982-12-14
    • US209488
    • 1980-11-24
    • Kazunari Shimizu
    • Kazunari Shimizu
    • G01R13/28G01R13/22G01R31/3177G06F11/25G09G1/08
    • G01R13/22G01R31/3177G06F11/25
    • A combined logic timing and state analyzer comprises an internally clocked, timing analyzer section receiving a first set of logic signals, and an externally clocked, state analyzer section receiving a second set of logic signals. The timing analyzer section samples the first set of logic signals, as well as the external clock signal associated with the second set of logic signals, at a rate determined by the internal clock pulses and stores the samples in a first set of memories. The state analyzer section samples the second set of logic signals at a rate determined by the external clock pulses and stores the samples in a second set of memories. Data introduction into the memories terminates when they are triggered, as in the event of a malfunction of the system being investigated. The logic analyzer further includes a display circuit for repetitively reading out the first and the second sets of memories and for causing a display device to visually present the output data of the first memory set in the form of a timing diagram and the output data of the second memory set in the form of a state table. The time relationship between the two display formats can be readily ascertained since the timing diagram includes a waveform, or other visual representations, indicative of the external clock pulses used for sampling the second set of logic signals.
    • 组合逻辑定时和状态分析器包括接收第一组逻辑信号的内部时钟定时分析器部分和接收第二组逻辑信号的外部时钟状态分析器部分。 定时分析器部分以由内部时钟脉冲确定的速率对第一组逻辑信号以及与第二组逻辑信号相关联的外部时钟信号进行采样,并将采样存储在第一组存储器中。 状态分析器部分以由外部时钟脉冲确定的速率对第二组逻辑信号进行采样,并将采样存储在第二组存储器中。 数据引入到存储器当它们被触发时终止,如在被调查的系统发生故障的情况下。 逻辑分析器还包括显示电路,用于重复地读出第一和第二组存储器,并且使得显示装置以时序图的形式可视地呈现第一存储器组的输出数据,并且输出数据 第二个内存以状态表的形式设置。 由于时序图包括指示用于对第二组逻辑信号进行采样的外部时钟脉冲的波形或其他视觉表示,所以可以容易地确定两种显示格式之间的时间关系。