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1. 发明授权

US6066961A Individually accessible macrocell 失效
标题翻译：可单独访问的宏单元
公开(公告)号：US6066961A
公开(公告)日：2000-05-23
申请号：US95808
申请日：1998-06-10
申请人： Ching Lee , Yoram Cedar
发明人： Ching Lee , Yoram Cedar
IPC分类号： G06F13/38 , G06F15/78 , H03K19/173 , H03K19/177 , H03K19/77
CPC分类号： H03K19/17744 , G06F15/7867 , H03K19/17704
摘要： A circuit connectable to a microcontroller having an address bus, a data bus, a read line and a write line include a programmable logic device (PLD) array, at least one input pin, at least two databus macrocells and a bit mask register. The input pin is connected to the PLD array and is connectable to the address bus. The databus macrocell is connected to the PLD array and to an external unit and is also connectable to the data bus, the read line and the write line. The bit mask register has at least two bits, each associated with one of the at least two macrocells. The databus can directly access the databus macrocell only if its associated bit in the bit mask register is of the correct state. In another embodiment, the write line carries an edge write signal and the databus accesses the databus macrocell on one edge of the edge write signal.
摘要翻译：可连接到具有地址总线，数据总线，读取线和写入线的微控制器的电路包括可编程逻辑器件（PLD）阵列，至少一个输入引脚，至少两个数据总线宏单元和位掩码寄存器。输入引脚连接到PLD阵列，可连接到地址总线。数据总线宏单元连接到PLD阵列和外部单元，并且还可连接到数据总线，读取线和写入线。位掩码寄存器具有至少两个位，每个位与至少两个宏单元中的一个相关联。数据总线只有在位掩码寄存器中的相关位处于正确状态时才能直接访问数据总线宏单元。在另一个实施例中，写入线携带边缘写入信号，并且数据总线在边缘写入信号的一个边缘上访问数据总线宏单元。

2. 发明授权

US5796313A Low power programmable ring oscillator 失效
标题翻译：低功耗可编程环形振荡器
公开(公告)号：US5796313A
公开(公告)日：1998-08-18
申请号：US639281
申请日：1996-04-25
申请人： Boaz Eitan
发明人： Boaz Eitan
IPC分类号： H03K3/03 , H03L1/00 , H03L3/00 , H03B5/04 , H03L5/00
CPC分类号： H03K3/0315 , H03L1/00 , H03L3/00
摘要： A novel ring oscillator integrated circuit whose frequency of oscillation is independent of supply voltage, temperature and process technology is described. In addition, the ring oscillator circuit consumes low power and its frequency of oscillation is programmable. The ring oscillator comprises one or more inverter sections cascaded together in series. The output of the final inverter stage is coupled to the input of the first inverter stage. Inserted in the feedback loop is feedback control circuitry which functions to control the start/stop operation of the oscillator. Each inverter section includes a p-channel transistor coupled to a parallel combination of impedance and capacitance, which gives the inverter section asymmetric operating characteristics. This asymmetry helps to achieve a frequency of oscillation independent of supply voltage. A plurality of transistors having predetermined impedance's are coupled in series with the p-channel transistor to form the current limiting impedance. An output buffer provides large drive capability and achieves low power consumption by eliminating normally present crowbar current during switching. Pull-down control circuitry provides individual gate control of each of the transistors making up the current limiter in each inverter section. Process independence is achieved by trimming the plurality of pull-down current limiting transistor so as to attain a particular frequency of oscillation.
摘要翻译：描述了一种新颖的环形振荡器集成电路，其振荡频率与电源电压，温度和工艺技术无关。此外，环形振荡器电路消耗低功耗，其振荡频率可编程。环形振荡器包括串联在一起的一个或多个逆变器部分。最后的逆变器级的输出耦合到第一逆变器级的输入端。插入反馈回路中的是反馈控制电路，其用于控制振荡器的启动/停止操作。每个逆变器部分包括耦合到阻抗和电容的并联组合的p沟道晶体管，这使得逆变器部分具有不对称的工作特性。这种不对称有助于实现独立于电源电压的振荡频率。具有预定阻抗的多个晶体管与p沟道晶体管串联耦合以形成限流阻抗。输出缓冲器提供大的驱动能力，通过消除切换期间正常出现的撬棒电流来实现低功耗。下拉控制电路在每个逆变器部分中提供构成电流限制器的每个晶体管的单独栅极控制。通过修整多个下拉限流晶体管以获得特定的振荡频率来实现过程独立性。

3. 发明授权

US5696730A First read cycle circuit for semiconductor memory 失效
标题翻译：半导体存储器的第一个读周期电路
公开(公告)号：US5696730A
公开(公告)日：1997-12-09
申请号：US665191
申请日：1996-06-13
申请人： Yaron Slezak , Boaz Eitan
发明人： Yaron Slezak , Boaz Eitan
IPC分类号： G11C11/41 , G11C7/22 , G11C8/18 , G11C16/06 , G11C7/00
CPC分类号： G11C7/22 , G11C8/18
摘要： A novel circuit for initiating a first read cycle when power is first applied to the memory device is disclosed. The circuit compares the ramping up of the word line voltage signal to a stable reference voltage using a comparator. Once the word line voltage reaches a predetermined level, but before it reaches its maximum value, the comparator trips. The transition of the comparator output is sensed by an address transition detection circuit which subsequently triggers a read cycle of the memory, thus creating a dummy read access without any requirement that the input address actually make a transition. A memory access time later, valid data is available at the output of the memory array. A voltage divider is used to divide the word line voltage to a suitable level for input to the comparator. The stable reference voltage serves as the source of the word line signal, besides being input to the comparator. A voltage multiplier is utilized to generate the word line signal from the voltage reference. Alternatively, the word line voltage may be supplied by an external source such as the supply voltage. Both the voltage multiplier and the voltage divider include programmable trimming transistors which allow tuning of their respective outputs. In addition, enable circuitry is included which disables the first read cycle circuitry in order to reduce power consumption after the first read cycle is initiated.
摘要翻译：公开了一种用于在首次向存储器件施加电力时启动第一读取周期的新型电路。该电路使用比较器将字线电压信号的上升与稳定的参考电压进行比较。一旦字线电压达到预定电平，但在达到其最大值之前，比较器跳闸。比较器输出的转换由地址转换检测电路感测，随后触发存储器的读取周期，从而创建虚拟读取访问，而不需要输入地址实际上进行转换。存储器访问时间之后，存储器阵列的输出端提供有效的数据。分压器用于将字线电压分成适当的电平以供输入到比较器。除了输入到比较器之外，稳定的参考电压也用作字线信号的源。利用电压倍增器从电压基准产生字线信号。或者，字线电压可以由诸如电源电压的外部源提供。电压倍增器和分压器都包括可调谐其各自输出的可编程微调晶体管。此外，包括启用电路，其禁用第一读取周期电路，以便在启动第一读取周期之后降低功耗。

4. 发明授权

US5034786A Opaque cover for preventing erasure of an EPROM 失效
标题翻译：用于防止擦除EPROM的不透明盖
公开(公告)号：US5034786A
公开(公告)日：1991-07-23
申请号：US214562
申请日：1988-07-01
申请人： Boaz Eitan
发明人： Boaz Eitan
IPC分类号： H01L29/788
CPC分类号： H01L29/7885
摘要： A structure for preventing light from reaching and erasing a floating gate comprises a control gate which covers not only the floating gate, but the portion of the semiconductor substrate laterally surrounding the floating gate. In accordance with one novel feature of my invention, a conductive structure also laterally surrounds the floating gate and extends between the semiconductor substrate and the control gate. In one embodiment, the conductive structure is electrically shorted to ground and is constructed from the same layer of material as the floating gate. Of importance, the conductive structure both serves as an additional light blocking structure and also serves as a field plate so that it is not necessary to form a thick field oxide layer surrounding the transistor. Because the conductive structure and the control gate are used as the light blocking structure and the contact metallization layer is not used to form the opaque cover, it is possible to extend contact metallization over the covered floating gate transistor.
摘要翻译：用于防止光到达和擦除浮动栅极的结构包括不仅覆盖浮动栅极而且半导体衬底的横向围绕浮动栅极的部分的控制栅极。根据本发明的一个新颖特征，导电结构还横向围绕浮动栅极并且在半导体衬底和控制栅极之间延伸。在一个实施例中，导电结构被电短路接地，并由与浮动栅极相同的材料层构成。重要的是，导电结构都用作附加的光阻挡结构，并且还用作场板，使得不需要形成围绕晶体管的厚的场氧化物层。由于导电结构和控制栅极用作遮光结构，并且接触金属化层不用于形成不透明盖，所以可以在覆盖的浮栅晶体管上扩展接触金属化。

5. 发明授权

US4649520A Single layer polycrystalline floating gate 失效
标题翻译：单层多晶浮栅
公开(公告)号：US4649520A
公开(公告)日：1987-03-10
申请号：US669198
申请日：1984-11-07
申请人： Boaz Eitan
发明人： Boaz Eitan
IPC分类号： H01L29/788 , G11C11/40
CPC分类号： H01L29/7885
摘要： A programmable read only memory includes a transistor having an N type source, an N type drain, and a polysilicon floating gate extending over the channel between the source and drain. The floating gate also extends over and is capacitively coupled to an N well. By applying an electric potential to the N well, the potential on the floating gate above the channel is altered.Within the N well is a P region, which mitigates the decrease in capacitive coupling between the N well and the floating gate caused by carrier depletion.
摘要翻译：可编程只读存储器包括具有在源极和漏极之间的沟道上延伸的N型源极，N型漏极和多晶硅浮动栅极的晶体管。浮动栅极也延伸并且电容耦合到N阱。通过向N阱施加电位，通道上方的浮动栅极上的电位被改变。在N阱内是P区，其减轻由载波耗尽引起的N阱和浮栅之间的电容耦合的减小。

6. 发明授权

US6072733A Programmable sense amplifier delay (PSAD) circuit which is matched to the memory array 失效
标题翻译：与存储器阵列匹配的可编程读出放大器延迟（PSAD）电路
公开(公告)号：US6072733A
公开(公告)日：2000-06-06
申请号：US953690
申请日：1997-10-17
申请人： Manik Advani
发明人： Manik Advani
IPC分类号： G11C7/06 , G11C7/22 , G11C16/26 , G11C7/00
CPC分类号： G11C16/26 , G11C7/067 , G11C7/22 , G11C7/04
摘要： A programmable sense amplifier delay (PSAD) circuit that is matched to the response of the memory array due to temperature and voltage supply Vcc. The circuit includes an inverter, a pull-up transistor, a pull-down transistor of the type of the cells of the memory array and a plurality of capacitors. The inverter responds to a predetermined voltage drop between the voltage level of the voltage source and the voltage on the input line. The pull-up transistor is connected between the voltage source Vcc and the input line and is activatable during a pre-charge phase of the memory array to raise the voltage level of the input line towards the voltage source. The pull-down transistor is connected between the input line and a ground source and is activatable after the pre-charge phase to discharge the voltage level of the input line. The capacitors are selectively connected in parallel to the pull-down transistor and define the speed at which the pull-down transistor discharges the input line. The invention also incorporates the voltage drop inverter.
摘要翻译：可编程读出放大器延迟（PSAD）电路，由于温度和电压Vcc而与存储器阵列的响应相匹配。电路包括反相器，上拉晶体管，存储器阵列的单元的类型的下拉晶体管和多个电容器。逆变器响应电压源的电压电平与输入线上的电压之间的预定电压降。上拉晶体管连接在电压源Vcc和输入线之间，并且可在存储器阵列的预充电阶段激活，以将输入线的电压电平升高到电压源。下拉晶体管连接在输入线和地源之间，并在预充电阶段后激活，以放电输入线的电压电平。电容器选择性地并联连接到下拉晶体管并且限定下拉晶体管放电输入线的速度。本发明还包括电压降逆变器。

7. 发明授权

US5912560A Charge pump circuit for voltage boosting in integrated semiconductor circuits 失效
标题翻译：集成半导体电路中的升压电荷泵电路
公开(公告)号：US5912560A
公开(公告)日：1999-06-15
申请号：US806560
申请日：1997-02-25
申请人： John H. Pasternak
发明人： John H. Pasternak
IPC分类号： H02M3/07 , H03K17/06 , H03K3/01
CPC分类号： H03K17/063 , H02M3/073
摘要： A charge pump whose charge transfer switches are formed of charge transfer transistors and single pole, double throw (SPDT) switches each of which controls the gate of its corresponding transistor. Each SPDT switch has two throw contacts, one which is connected to the left diffusion of its corresponding charge transfer transistor and the other of which is connected to ground. Thus, the SPDT switch selectively connects the gate of the charge transfer transistor it controls between a diode connection (the first contact) and ground (the second contact). As a result, the charge transfer switches of the present invention are both fully on (when diode-connected) or fully off (when connected to ground).
摘要翻译：一种电荷泵，其电荷转移开关由电荷转移晶体管和单极双掷（SPDT）开关形成，每个开关控制其相应晶体管的栅极。每个SPDT开关具有两个触点，一个连接到其相应的电荷转移晶体管的左扩散，另一个连接到地。因此，SPDT开关选择性地将其控制的电荷转移晶体管的栅极连接在二极管连接（第一触点）和地（第二触点）之间。结果，本发明的电荷转移开关全部接通（二极管连接时）或完全断开（当接地时）。

8. 发明授权

US5783964A Backup battery switch with first power up control 失效
标题翻译：备用电池开关，首次上电控制
公开(公告)号：US5783964A
公开(公告)日：1998-07-21
申请号：US749616
申请日：1996-11-18
申请人： Boaz Eitan
发明人： Boaz Eitan
IPC分类号： G11C5/14 , H02J9/06 , H03K17/22 , H03K17/693 , H03K17/62
CPC分类号： H03K17/223 , G11C5/141 , H02J9/061 , H03K17/22 , H03K17/693
摘要： A switching circuit for switching between a main power supply and a battery power supply only after first power up includes a switch, a first power up transfer transistor and a first power up latch. The switch switches between the main and battery power supplies and provides one of the main and battery power supplies to a switched power supply node. The first power-up transfer transistor is connected on input to the switched power supply node. The first power up latch is powered by a switched power supply from the switched power supply node and is connected on output to a gate of the first power-up transfer transistor. The first power up latch produces an activation signal to the gate upon and after first power up of the main power supply.
摘要翻译：仅在第一次通电之后，用于在主电源和电池电源之间切换的开关电路包括开关，第一上电传输晶体管和第一上电锁存器。开关在主电源电源和电池电源之间切换，并为开关电源节点提供主电源电源和电池电源之一。第一上电传输晶体管连接到开关电源节点的输入端。第一上电锁存器由来自开关电源节点的开关电源供电，并且在输出端连接到第一上电传输晶体管的栅极。第一上电锁存器在主电源的第一次上电之后和之后产生到门的激活信号。

9. 发明授权

US5683925A Manufacturing method for ROM array with minimal band-to-band tunneling 失效
标题翻译：具有最小带到带隧道的ROM阵列的制造方法
公开(公告)号：US5683925A
公开(公告)日：1997-11-04
申请号：US665150
申请日：1996-06-13
申请人： Rustom F. Irani , Reza Kazerounian , Mark Michael Nelson
发明人： Rustom F. Irani , Reza Kazerounian , Mark Michael Nelson
IPC分类号： H01L21/8246
CPC分类号： H01L27/112 , Y10S148/116 , Y10S438/981
摘要： A method of manufacturing a ROM array to minimize band-to-band tunneling is described. The method includes the steps of: a) implanting bit lines into the core area of a substrate as per a later-removed bit line mask, b) providing a ROM oxide layer over the entirety of the substrate, c) etching the ROM oxide layer only from the periphery area as per a later-removed core protect mask, d) providing a gate oxide layer over the entirety of the ROM array, e) laying down polysilicon rows in the core area as per a polysilicon mask and f) implanting a ROM implant into selected areas of the core area, thereby to produce turned off core transistors. The thickness of the gate oxide layer and the ROM oxide layer are independent of each other.
摘要翻译：描述了一种制造ROM阵列以最小化频带隧穿的方法。该方法包括以下步骤：a）根据稍后去除的位线掩模将位线注入衬底的芯区域，b）在整个衬底上提供ROM氧化层，c）蚀刻ROM氧化物层 d）在ROM阵列整体上提供栅极氧化层，e）根据多晶硅掩模放置芯区域中的多晶硅行，以及f）植入一个 ROM注入核心区域的选定区域，从而产生截止的核心晶体管。栅极氧化物层和ROM氧化物层的厚度彼此独立。

10. 发明授权

US5682353A Self adjusting sense amplifier clock delay circuit 失效
标题翻译：自调音放大器时钟延时电路
公开(公告)号：US5682353A
公开(公告)日：1997-10-28
申请号：US665151
申请日：1996-06-13
申请人： Boaz Eitan , Larry Willis Petersen , Yaron Slezak
发明人： Boaz Eitan , Larry Willis Petersen , Yaron Slezak
IPC分类号： G11C11/41 , G11C7/06 , G11C8/18 , G11C16/06 , G11C8/00
CPC分类号： G11C7/06 , G11C8/18
摘要： A clock delay circuit for generating a delay for a sense amplifier release signal in an integrated circuit semiconductor memory device is disclosed. Rather than utilize traditional programmable capacitors that must be trimmed on a die by die basis, the novel clock delay circuit disclosed utilizes a small ROM, EPROM, EEPROM or FLASH array coupled to a bit line emulator to provide a clock delay matched to the larger main array. The size of the small memory array is on the order of 5 to 10 bit lines by 5 to 10 word lines. One cell within the small array is fixed to be continuously selected. The selected cell is coupled to the clock delay node along with the bit line emulator. The bit line emulator models the capacitance of the actual bit line used in the main array. However, the circuit is constructed so that a much larger signal is generated by the delay circuit such that sense amplifiers detect the correct signal. The CMOS based clock delay circuit uses the emulated array to generate a delta or margin that accurately tracks the delays within the main array with variations in temperature, supply voltage and process.
摘要翻译：公开了一种用于在集成电路半导体存储器件中产生读出放大器释放信号的延迟的时钟延迟电路。公开的新颖的时钟延迟电路不是利用必须通过芯片在芯片上修整的传统可编程电容器，而是利用耦合到位线仿真器的小型ROM，EPROM，EEPROM或闪存阵列来提供与较大的主器件匹配的时钟延迟数组。小存储器阵列的大小是5到10个位线的5到10个字线。小阵列中的一个单元被固定为连续选择。所选择的单元与位线仿真器一起耦合到时钟延迟节点。位线仿真器模拟主阵列中使用的实际位线的电容。然而，电路被构造成使得延迟电路产生大得多的信号，使得读出放大器检测正确的信号。基于CMOS的时钟延迟电路使用仿真阵列来产生增量或余量，以便在温度，电源电压和过程的变化下精确跟踪主阵列内的延迟。

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