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1. 发明授权

US5683925A Manufacturing method for ROM array with minimal band-to-band tunneling 失效
标题翻译：具有最小带到带隧道的ROM阵列的制造方法
公开(公告)号：US5683925A
公开(公告)日：1997-11-04
申请号：US665150
申请日：1996-06-13
申请人： Rustom F. Irani , Reza Kazerounian , Mark Michael Nelson
发明人： Rustom F. Irani , Reza Kazerounian , Mark Michael Nelson
IPC分类号： H01L21/8246
CPC分类号： H01L27/112 , Y10S148/116 , Y10S438/981
摘要： A method of manufacturing a ROM array to minimize band-to-band tunneling is described. The method includes the steps of: a) implanting bit lines into the core area of a substrate as per a later-removed bit line mask, b) providing a ROM oxide layer over the entirety of the substrate, c) etching the ROM oxide layer only from the periphery area as per a later-removed core protect mask, d) providing a gate oxide layer over the entirety of the ROM array, e) laying down polysilicon rows in the core area as per a polysilicon mask and f) implanting a ROM implant into selected areas of the core area, thereby to produce turned off core transistors. The thickness of the gate oxide layer and the ROM oxide layer are independent of each other.
摘要翻译：描述了一种制造ROM阵列以最小化频带隧穿的方法。该方法包括以下步骤：a）根据稍后去除的位线掩模将位线注入衬底的芯区域，b）在整个衬底上提供ROM氧化层，c）蚀刻ROM氧化物层 d）在ROM阵列整体上提供栅极氧化层，e）根据多晶硅掩模放置芯区域中的多晶硅行，以及f）植入一个 ROM注入核心区域的选定区域，从而产生截止的核心晶体管。栅极氧化物层和ROM氧化物层的厚度彼此独立。

2. 发明授权

US5910016A Scalable EPROM array 失效
标题翻译：可扩展EPROM阵列
公开(公告)号：US5910016A
公开(公告)日：1999-06-08
申请号：US806559
申请日：1997-02-25
申请人： Reza Kazerounian , Rustom F. Irani , Boaz Eitan
发明人： Reza Kazerounian , Rustom F. Irani , Boaz Eitan
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L21/336
CPC分类号： H01L27/11521 , G11C16/0491 , H01L27/115
摘要： An electrically programmable read-only memory (EPROM) array having self-aligned thick oxide isolation units, and a method for manufacturing the EPROM array are disclosed. The EPROM array is formed of EPROM areas having EPROM cells and control areas, two per EPROM area. Each control area includes at least one row and each row includes a first polysilicon strip, a second polysilicon strip lying on top of and perpendicular to the first polysilicon strip, and alternating thick and thin oxide elements under the first polysilicon strip. The thick and thin oxide elements are self-aligned to the first polysilicon strip. The thin oxide and the first and second polysilicon strips form a select transistor. The thick oxide and the first and second polysilicon strips form a novel self-aligned thick oxide isolation unit.
摘要翻译：公开了一种具有自对准厚氧化物隔离单元的电可编程只读存储器（EPROM）阵列和用于制造EPROM阵列的方法。 EPROM阵列由具有EPROM单元和控制区域的EPROM区域形成，每个EPROM区域两个。每个控制区域包括至少一行，并且每行包括第一多晶硅条，位于第一多晶硅条的顶部并垂直于第一多晶硅条的第二多晶硅条，以及在第一多晶硅条下面交替的厚的和薄的氧化物元件。厚且薄的氧化物元件与第一多晶硅条自对准。薄氧化物和第一和第二多晶硅条形成选择晶体管。厚氧化物和第一和第二多晶硅条形成新的自对准厚氧化物隔离单元。

3. 发明授权

US5623443A Scalable EPROM array with thick and thin non-field oxide gate insulators 失效
标题翻译：具有厚而薄的非场氧化物栅极绝缘体的可扩展EPROM阵列
公开(公告)号：US5623443A
公开(公告)日：1997-04-22
申请号：US212165
申请日：1994-03-11
申请人： Reza Kazerounian , Rustom F. Irani , Boaz Eitan
发明人： Reza Kazerounian , Rustom F. Irani , Boaz Eitan
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , G11C16/06
CPC分类号： H01L27/11521 , G11C16/0491 , H01L27/115
摘要： An electrically programmable read-only memory (EPROM) array having self-aligned thick oxide isolation units, and a method for manufacturing the EPROM array are disclosed. The EPROM array is formed of EPROM areas having EPROM cells and control areas, two per EPROM area. Each control area includes at least one row and each row includes a first polysilicon strip, a second polysilicon strip lying on top of and perpendicular to the first polysilicon strip, and alternating thick and thin oxide elements under the first polysilicon strip. The thick and thin oxide elements are self-aligned to the first polysilicon strip. The thin oxide and the first and second polysilicon strips form a select transistor. The thick oxide and the first and second polysilicon strips form a novel self-aligned thick oxide isolation unit.
摘要翻译：公开了一种具有自对准厚氧化物隔离单元的电可编程只读存储器（EPROM）阵列和用于制造EPROM阵列的方法。 EPROM阵列由具有EPROM单元和控制区域的EPROM区域形成，每个EPROM区域两个。每个控制区域包括至少一行，并且每行包括第一多晶硅条，位于第一多晶硅条的顶部并垂直于第一多晶硅条的第二多晶硅条，以及在第一多晶硅条下面交替的厚的和薄的氧化物元件。厚且薄的氧化物元件与第一多晶硅条自对准。薄氧化物和第一和第二多晶硅条形成选择晶体管。厚氧化物和第一和第二多晶硅条形成新的自对准厚氧化物隔离单元。

4. 发明授权

US5151375A EPROM virtual ground array 失效
标题翻译： EPROM虚拟接地阵列
公开(公告)号：US5151375A
公开(公告)日：1992-09-29
申请号：US537553
申请日：1990-06-13
申请人： Reza Kazerounian , Boaz Eitan , Rustom F. Irani
发明人： Reza Kazerounian , Boaz Eitan , Rustom F. Irani
IPC分类号： H01L21/8247 , H01L23/528 , H01L23/535
CPC分类号： H01L27/11521 , H01L23/528 , H01L23/535 , H01L2924/0002
摘要： An electrically programmable read only memory contains alternating metal bit lines and diffused bit lines. Each diffused bit line is broken into a plurality of segments. Each of the segments of the diffused bit line comprises a virtual source. A multiplicity of floating gate transistors are arranged in rows and columns. The floating gate transistors in each column are divided into M groups of N floating gate transistors each. The floating gate transistors in the n.sup.th and the (n+1).sup.th columns, where n is an odd integer given by 1.ltoreq.n.ltoreq.N and (N+1) is the maximum number of columns in the array are connected to the segments of one diffused bit line placed between the n.sup.th and the (n+1).sup.th columns. At least one first transfer transistor is arranged to connect one segment comprising a virtual source to a first metal bit line. The first metal bit line functions as the source for the N floating gate transistors in the (n+1).sup.th column connected to said one segment. At least one second transfer transistor connects the same one segment comprising a virtual source to a second metal bit line. The second metal bit line functions as a source for the N floating gate transistors in the n.sup.th column connected to said one segment. The removal of each select transistor from the cell where it previously resided in series with its corresponding floating gate transistor, and the combining of a plurality of select transistors into one select transistor substantially reduces the area taken by each memory cell in the array.
摘要翻译：电可编程只读存储器包含交替的金属位线和扩散位线。每个扩散位线被分解成多个段。扩散位线的每个段包括虚拟源。多个浮栅晶体管以行和列布置。每列中的浮栅晶体管分为M组N个浮栅晶体管。第n和第（n + 1）列中的浮置栅极晶体管，其中n是由1

5. 发明授权

US5838046A Operating method for ROM array which minimizes band-to-band tunneling 失效
标题翻译： ROM阵列的操作方法，使带通隧道最小化
公开(公告)号：US5838046A
公开(公告)日：1998-11-17
申请号：US665136
申请日：1996-06-13
申请人： Rustom F. Irani , Boaz Eitan , Mark Michael Nelson , Larry Willis Petersen
发明人： Rustom F. Irani , Boaz Eitan , Mark Michael Nelson , Larry Willis Petersen
IPC分类号： G11C17/12 , H01L29/76
CPC分类号： G11C17/12
摘要： A read only memory (ROM) array is disclosed which includes a) a voltage supply providing an operating voltage level, b) a plurality of word-lines, c) a multiplicity of ROM transistors, and d) a word-line clamper. The ROM transistors are divided into turned on and turned off transistors. Each ROM transistor has a gate connected to one of the word-lines, a gate oxide beneath the gate, whose thickness is less than 250 .ANG., and a channel beneath the gate oxide. The turned off transistors additionally have a ROM implant in their channel whose dosage is no larger than the amount which generates a predetermined desired minimal band-to-band tunneling current The ROM implant and gate oxide thickness define a threshold voltage for the tamed off tranistors, the threshold voltage being less than the operating voltage level. The word-line damper provides a word-line voltage to each of the word-lines, the word-line voltage being clamped to a voltage level no higher than the threshold voltage of the turned off transistor.
摘要翻译：公开了一种只读存储器（ROM）阵列，其包括a）提供工作电压电平的电压源，b）多个字线，c）多个ROM晶体管，以及d）字线钳位器。 ROM晶体管分为导通和截止晶体管。每个ROM晶体管具有连接到字线之一的栅极，栅极下方的栅极氧化物，其厚度小于250，栅极氧化物下方的沟道。关闭晶体管另外在其通道中具有ROM植入物，其剂量不大于产生预定的期望的最小带 - 带隧穿电流的量。ROM注入和栅极氧化物厚度限定了驯化的晶体管的阈值电压，阈值电压小于工作电压电平。字线阻尼器对每个字线提供字线电压，字线电压被钳位到不高于截止晶体管的阈值电压的电压电平。

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